Semiconductor Package Composite Conductive Structures
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving smaller footprints and enhanced electrical performance, particularly in forming semiconductor packages with improved electrical performance and design flexibility.
Innovation Solution
The method involves forming composite conductive structures with through-substrate vias (TSVs) and anisotropic conductive adhesive layers, which are stacked to create a semiconductor package with a redistribution structure and insulating encapsulation, allowing for finer via pitch interconnections and structural support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging techniques are used, then manufacturing simplicity is maintained, but electrical performance and design flexibility are limited
Solution Approach 1:
The packaging structure is divided into multiple functional layers including support layers, conductive adhesive layers with TSVs, and insulating encapsulation layers. Each layer performs a specific function, allowing complex electrical interconnections while maintaining manufacturability through standardized layer fabrication processes
Solution Approach 2:
The patent transitions from planar interconnections to three-dimensional vertical interconnections using stacked composite conductive structures. Through-substrate vias enable electrical connections through the substrate thickness, adding a vertical dimension that improves electrical performance without increasing footprint area
2Ease of manufacture
If larger package footprints are used, then manufacturing is simpler, but device size and integration density increase
Solution Approach 1:
The patent utilizes vertical stacking of composite conductive structures to achieve complex interconnections in the thickness direction rather than requiring large lateral areas. This three-dimensional arrangement enables fine pitch interconnections without increasing the package footprint, addressing the need for smaller device sizes
Solution Approach 2:
Multiple functional layers are nested within each other, with conductive adhesive layers containing TSVs embedded within insulating encapsulation layers. This nested arrangement maximizes the use of vertical space, enabling complex electrical interconnections within a compact footprint
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of semiconductor packages with improved electrical performance and design flexibility, achieving finer pitch interconnections and structural integrity, thereby addressing the need for smaller and more efficient packaging.
Implementation Method 1
an anisotropic conductive member underlying the support layer and the TMVs
Data Source
AI summary
A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first redistribution structure, a semiconductor die disposed on the first redistribution structure, a stack of composite conductive structures disposed on the first redistribution structure, and an insulating encapsulation disposed on the first redistribution structure and laterally covering the semiconductor die and the stack of composite conductive structures. The stack of composite conductive structures includes a lower tier and an upper tier stacked upon the lower tier. Each of the lower tier and the upper tier includes a support layer, through material vias (TMVs) penetrating through the support layer, and a conductive adhesive member underlying the support layer and the TMVs.