Power Semiconductor Package with Conductive Adhesive

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Solution Overview

Problem

The miniaturization of semiconductor dies poses challenges in achieving efficient electrical and thermal performance due to design constraints, contamination risks from lead-free solders, mechanical damage during soldering, and tracking distance issues, especially in high-voltage applications like IGBTs for automotive use.

Innovation Solution

A semiconductor package using a substrate with a support plate, insulation body, and laterally spaced conductive pads, where electrodes are coupled using conductive adhesives, allowing for direct connections and external mounting, and optionally featuring a conductive strap for additional mechanical integration and thermal management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If the die size is reduced to improve integration density, then the area of the die is reduced, but the ability to achieve large cross-sectional area joints for electrical and thermal performance deteriorates

Engineering Contradiction:
Improvedie areaVSAvoidelectrical and thermal connection reliability
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The patent transitions from planar connections to three-dimensional stacked connections. Multiple dies are connected vertically through conductive adhesives and solder bumps, creating interlayer connections that provide large cross-sectional areas for electrical and thermal paths without increasing the lateral die area. This vertical dimensionality resolves the contradiction by maintaining connection reliability while enabling die miniaturization.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a stacked configuration where multiple dies are nested vertically one on top of another. Each die is connected to the layer below through conductive adhesive layers and solder bumps, creating a compact three-dimensional structure. This nesting approach allows large cross-sectional area joints to be achieved in the vertical direction while keeping individual die areas small.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Volume of moving object

If the die is made thinner to reduce package size, then the volume of the die is reduced, but the mechanical strength during soldering deteriorates

Engineering Contradiction:
Improvedie volumeVSAvoidmechanical strength during soldering
Core Design Contradiction:
Volume of moving objectVSStrength

Solution Approach 1:

The patent combines multiple thin dies into a stacked assembly where the collective structure provides enhanced mechanical strength. The conductive adhesive layers and solder bumps create a integrated multi-layer structure that distributes mechanical stresses during soldering across multiple bonding interfaces, preventing damage to individual thin dies while maintaining reduced overall volume.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent uses conductive adhesive layers as cushioning elements between the thin dies and the solder joints. These adhesive layers absorb and distribute mechanical stresses during the soldering process, protecting the fragile thin dies from damage. The adhesive layers act as shock-absorbing interfaces that maintain structural integrity throughout assembly.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Reliability

If larger tracking distances are implemented to meet high-voltage insulation standards, then the electrical insulation performance is improved, but the area occupied by the package increases

Engineering Contradiction:
Improveelectrical insulation performanceVSAvoidpackage area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent moves insulation and tracking distance requirements from the lateral plane to the vertical dimension. By stacking dies and connections vertically, the package achieves required electrical insulation distances through layer separation and vertical spacing rather than lateral expansion. This allows high-voltage insulation performance to be maintained while keeping the package footprint compact.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent uses thin insulating layers and encapsulation structures to provide electrical isolation between high-voltage and low-voltage regions. The insulation body and encapsulant materials create effective electrical barriers with minimal thickness, achieving required tracking distances without occupying excessive package area. These thin film structures provide efficient insulation in the vertical direction.

Inventive Principle:
Principle #30Flexible shells and thin films

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enables reliable assembly and efficient thermal and electrical performance, accommodating smaller die sizes and high-voltage applications while maintaining mechanical integrity and reducing contamination risks, and allows for flexible redistribution of contacts to meet surface insulation requirements.

Implementation Method 1

a first region electrically and mechanically coupled to the first electrode with a conductive adhesive body interposed between the first electrode and the first region

Methodology Applied
Scientific EffectConductive adhesive bonding: Adhesive

Implementation Method 2

a first region electrically and mechanically coupled to the first electrode with a conductive adhesive body interposed between the first electrode and the first region

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS9054090B2Power semiconductor package
Publication Date: 2015.06.09 INFINEON TECHNOLOGIES AMERICAS CORP
  • US9054090B2 patent drawing
  • US9054090B2 patent drawing
  • US9054090B2 patent drawing

AI summary

A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive.