Semiconductor Package Conductive Pillar Interconnect
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturizing packages while maintaining high functionality and reliability, particularly in reducing solder joint size to prevent electrical shorts and improving connection density without compromising performance.
Innovation Solution
The use of conductive pillars to connect redistribution structures to routing substrates reduces solder usage, minimizing the risk of electrical shorts and allowing for increased connection density, combined with the incorporation of electronic devices like IPDs or IVRs for enhanced functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If solder joint size is reduced to enable package miniaturization, then package size is reduced, but risk of electrical shorts between adjacent contacts increases
Solution Approach 1:
A planarization layer is introduced as an intermediary between adjacent solder joints. This layer fills the valleys between solder joints and provides a flat surface, effectively isolating adjacent solder joints from each other and preventing electrical shorts while allowing the use of smaller solder joints for package miniaturization.
Solution Approach 2:
The planarization layer is applied in advance before final packaging, creating a protective barrier that cushions and isolates adjacent solder joints. This beforehand cushioning prevents potential electrical shorts before they can occur, enabling safer use of reduced solder joint sizes.
2Productivity
If connection density is increased to improve functionality, then functional density is improved, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct stages: forming solder joints, applying the planarization layer, and subsequent packaging. This segmentation allows each stage to be optimized independently, enabling high connection density while managing manufacturing complexity through standardized, repeatable processes.
Solution Approach 2:
The planarization layer changes the surface topology parameter from uneven (with valleys between solder joints) to flat. This parameter change enables increased connection density by allowing solder joints to be placed closer together while maintaining electrical isolation, thus improving functional density without proportionally increasing manufacturing complexity.
3Productivity
If more input/output pads are integrated to improve functionality, then functional density is improved, but package area increases
Solution Approach 1:
The planarization layer introduces a new dimensional element (the thickness of the planarization layer) that allows for vertical isolation of electrical signals. This enables horizontal packing of more I/O pads in the same package area by providing electrical isolation through the vertical dimension, thus improving functional density without increasing package area.
Data Source
AI summary
A semiconductor package includes an interconnect structure including a redistribution structure, an insulating layer over the redistribution structure, and conductive pillars on the insulating layer, wherein the conductive pillars are connected to the redistribution structure, wherein the interconnect structure is free of active devices, a routing substrate including a routing layer over a core substrate, wherein the interconnect structure is bonded to the routing substrate by solder joints, wherein each of the solder joints bonds a conductive pillar of the conductive pillars to the routing layer, an underfill surrounding the conductive pillars and the solder joints, and a semiconductor device including a semiconductor die connected to a routing structure, wherein the routing structure is bonded to an opposite side of the interconnect structure as the routing substrate.