Stacked Semiconductor Package with Conductive Pillars and In-FAB RDL
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high electrical performance and compact size due to the limitations of conventional packaging techniques, which often result in performance deterioration from high-temperature processes and complex fabrication processes.
Innovation Solution
A semiconductor package design featuring a redistribution substrate with stacked semiconductor chips, utilizing conductive pillars and external connection members, and a redistribution layer formed through an In-FAB process to reduce vertical distances and simplify fabrication, thereby improving electrical properties and reducing package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging techniques are used, then manufacturing simplicity is maintained, but electrical performance deteriorates due to high-temperature processes
Solution Approach 1:
The patent segments the packaging process into two distinct temperature regimes: In-FAB process (low temperature, compatible with chip fabrication) and Post-FAB process (high temperature, for final packaging). This segmentation allows electrical performance-critical components to be processed at low temperatures while still achieving complete packaging functionality.
Solution Approach 2:
The redistribution layer is formed through In-FAB process before the chip is completed, performing preliminary electrical connection work at low temperature. This preliminary action prevents the need for subsequent high-temperature reprocessing that would damage sensitive electrical structures.
2Volume of moving object
If conventional packaging techniques are used, then fabrication simplicity is maintained, but device size increases
Solution Approach 1:
The patent merges the redistribution layer formation with the chip fabrication process itself (In-FAB process), combining what were previously separate operations into a unified low-temperature process. This integration reduces overall package size while the modular division into In-FAB and Post-FAB stages manages fabrication complexity.
Solution Approach 2:
The patent transitions from planar packaging to three-dimensional stacked architecture, utilizing vertical space to reduce the package footprint. The conductive pillars extend vertically to connect stacked chips, enabling compact high-density integration.
3Volume of moving object
If vertical distance between chips is reduced, then package compactness is improved, but manufacturing precision requirements increase
Solution Approach 1:
The molding compound acts as an intermediary material that fills and stabilizes the spaces between stacked chips and conductive pillars. This intermediary enables reduced vertical spacing while compensating for manufacturing tolerances through its flow and encapsulation properties.
Solution Approach 2:
The patent changes the temperature parameter during fabrication (low temperature In-FAB process) to enable more flexible material behavior and reduced thermal expansion differences, thereby achieving reduced vertical distances with relaxed precision requirements compared to conventional high-temperature processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances electrical performance and compactness by minimizing vertical distances and simplifying the fabrication process, preventing performance deterioration from high-temperature heat, and allowing for a more efficient and compact semiconductor package.
Implementation Method 1
a plurality of conductive pillars that electrically connect the external connection members to the redistribution substrate
Implementation Method 2
each of the external connection members including a conductive bump pattern and a solder pattern on the conductive bump pattern
Data Source
AI summary
A semiconductor package includes a redistribution substrate having first and second surfaces, a first semiconductor chip on the first surface, external terminals on the second surface, a second semiconductor chip above the first semiconductor chip, external connection members below the second semiconductor chip, conductive pillars electrically connecting the external connection members to the redistribution substrate. The second semiconductor chip includes a device layer, a wiring layer, and a redistribution layer on a semiconductor substrate. The wiring layer includes intermetallic dielectric layers, wiring lines, and a conductive pad connected to an uppermost wiring line. The redistribution layer includes a first redistribution dielectric layer, a first redistribution pattern, and a second redistribution dielectric layer. A vertical distance between the semiconductor substrate and the conductive pillars is less than that between the first semiconductor chip and the external terminals.