Semiconductor Package Conductive Post Structure for Dense Chip Stacking
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Solution Overview
Problem
The challenge in semiconductor packaging lies in constructing a reliable wiring structure and dissipating heat effectively, particularly when multiple semiconductor chips are integrated on a single package, as the size of semiconductor chips decreases, making it difficult to attach and handle solder balls and requiring diverse board sizes, which complicates the integration and testing process.
Innovation Solution
A semiconductor package is fabricated using a method that involves a substrate with a seed layer, a sacrificial layer, and a photoimageable layer, where penetration holes are formed to create conductive posts that connect redistribution substrates, allowing for improved electrical connections and heat dissipation through a structured conductive post design with specific dimensions and materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chip size is reduced to increase integration density, then more chips can be mounted on a single package, but it becomes increasingly difficult to attach and handle solder balls and to perform testing
Solution Approach 1:
The patent divides the package structure into multiple redistribution substrates (first and second redistribution substrates) with separate bonding pads for solder balls. This segmentation allows each substrate to have its own dedicated solder ball attachment areas, making it easier to handle and attach solder balls even when multiple semiconductor chips are integrated on a single package.
2Quantity of substance
If multiple semiconductor chips are integrated on a single package, then packaging density increases, but constructing a reliable wiring structure and dissipating heat effectively becomes more difficult
Solution Approach 1:
The patent introduces a vertical stacking architecture with first and second redistribution substrates positioned at different heights, connected through conductive posts that extend vertically. This three-dimensional wiring structure allows for reliable electrical connections between multiple chips stacked vertically, solving the wiring complexity issue that arises when integrating multiple chips on a single package plane.
Solution Approach 2:
The patent employs mold-through vias (MTVs) as intermediary conductive structures that penetrate the mold layer to establish electrical connections between the first and second redistribution substrates. These MTVs serve as mediators that enable reliable signal and power transmission across multiple packaging layers, ensuring wiring reliability in densely integrated packages.
3Quantity of substance
If multiple semiconductor chips are integrated on a single package, then integration density increases, but heat dissipation becomes more challenging
Solution Approach 1:
The patent utilizes vertical conductive posts and mold-through vias to create three-dimensional heat dissipation pathways. Heat generated by multiple semiconductor chips can be conducted vertically through the conductive posts and MTVs to the substrate, providing efficient thermal management in densely integrated packages by moving heat away from the chip stack in the vertical dimension.
Data Source
AI summary
A method of fabricating a semiconductor package may include providing a substrate, forming a seed layer to cover a top surface of the substrate, sequentially stacking a sacrificial layer and a photoimageable layer on the seed layer, forming a penetration hole to penetrate the photoimageable layer and the sacrificial layer and expose the seed layer, forming a conductive post in the penetration hole, performing a first process to remove at least a portion of the sacrificial layer, performing a second process to remove the photoimageable layer, and patterning or removing the seed layer.