Semiconductor Package Conductive Posts and Encapsulant Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional package on package (PoP) structures using solder balls for interconnection face limitations in miniaturization, I/O density, and moisture susceptibility due to large pitch and height requirements, as well as the absence of encapsulation between substrates.
Innovation Solution
A semiconductor package utilizing conductive posts instead of solder balls, with an encapsulant formed between the packaging substrate and the electronic element to protect against moisture, and the upper surfaces of the encapsulant and conductive posts being flush with the chip's inactive surface to reduce thickness and increase density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder balls are used as interconnection structure, then electrical connection between substrates is achieved, but the pitch between solder balls must be greater than 300 um to prevent solder bridging, which occupies large area and limits I/O density
Solution Approach 1:
The patent changes the interconnection structure from spherical solder balls to cylindrical conductive posts with flat tops. This geometric parameter change allows the posts to be arranged in a grid pattern with smaller pitch (less than 300 um) while preventing bridging through their cylindrical shape and flat upper surfaces, thereby increasing I/O density without sacrificing reliability
2Reliability
If solder balls are used for interconnection, then electrical connection is established, but the structure height increases and cannot be effectively reduced
Solution Approach 1:
The patent replaces spherical solder balls with cylindrical conductive posts that have a more favorable height-to-diameter ratio. The posts extend vertically from the lower substrate and can be integrated with the upper substrate or electronic element, reducing the overall package thickness while maintaining the electrical interconnection function
3Ease of manufacture
If no encapsulant is formed between lower packaging substrate and upper electronic element, then processing is simplified, but chips and interconnection structure are susceptible to intrusion of moisture
Solution Approach 1:
The patent applies preliminary action by forming the encapsulant material between the lower packaging substrate and the upper electronic element during the packaging process. This encapsulant layer is applied in advance to protect the chips and interconnection structures from moisture intrusion before the final assembly is completed, thereby preventing harmful effects without significantly complicating the manufacturing process
Data Source
AI summary
A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture.