Semiconductor Package Conductive Posts Eliminate Underfill
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Solution Overview
Problem
The CTE mismatch between semiconductor chips and packaging substrates leads to delamination, warpage, and reduced reliability in flip-chip packaging, and the use of silicon interposers with pre-formed bumps is prone to cracking due to thermal stresses.
Innovation Solution
A semiconductor package with conductive posts formed by electroplating through holes in the substrate, directly connecting the semiconductor chip, which reduces joint interfaces and eliminates the need for underfilling, thereby enhancing reliability and reducing fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a silicon interposer with pre-formed bumps is used to connect the semiconductor chip to the substrate, then the CTE mismatch problem is solved, but thermal stresses cause cracking at the multiple joint interfaces between the UBM layer, metal post, nickel layer, and bumps
Solution Approach 1:
The patent merges multiple separate layers (UBM layer, metal post, nickel layer) into a single integrated conductive post structure. This eliminates the multiple joint interfaces between these layers and the bump, reducing the number of potential cracking sites while maintaining the CTE matching function.
Solution Approach 2:
The patent extracts and eliminates the bump structure from the connection system. By removing the bump and its associated multiple metallurgical layers, the invention reduces the complexity of joint interfaces and the associated thermal stress cracking risks, while still achieving reliable electrical and mechanical connection through the simplified conductive post.
2Reliability
If multiple joint interfaces are formed between the electrode pads and the bumps through UBM layer, metal post, and nickel layer, then electrical connection is achieved, but cracking occurs at these interfaces due to thermal stresses
Solution Approach 1:
The patent combines multiple separate metallurgical layers into a single integrated conductive post, eliminating the multiple joint interfaces that are susceptible to thermal stress cracking. This merged structure maintains electrical connectivity while reducing the harmful effects of thermal cycling.
3Reliability
If underfill is formed between the semiconductor chip and the silicon interposer, then delamination is prevented, but the fabrication process becomes more complex and time-consuming
Solution Approach 1:
The patent extracts and eliminates the underfill step from the fabrication process. By designing the conductive post to directly connect the chip to the substrate without requiring an intermediate silicon interposer and underfill layer, the invention simplifies the manufacturing process while maintaining structural integrity and preventing delamination.
4Ease of manufacture
If pre-formed bumps are used on the silicon interposer, then the chip can be disposed on the interposer, but the bumps are prone to cracking due to temperature variation during fabrication
Solution Approach 1:
The patent removes the pre-formed bump structure from the manufacturing process. By eliminating the bump and its associated multiple metallurgical layers, the invention avoids the thermal stress cracking issues that occur during temperature variations in fabrication, while still achieving reliable chip mounting through the simplified conductive post structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces cracking at joint interfaces, improves product reliability, and shortens fabrication time by eliminating the underfilling process while providing structural protection with an encapsulant.
Implementation Method 1
A plurality of conductive posts penetrating the first and second surfaces of the semiconductor substrate and the adhesive layer and electrically connected to the semiconductor chip
Data Source
AI summary
A semiconductor package is provided, which includes: a semiconductor substrate having opposite first and second surfaces; an adhesive layer formed on the first surface of the semiconductor substrate; at least a semiconductor chip disposed on the adhesive layer; an encapsulant formed on the adhesive layer for encapsulating the semiconductor chip; and a plurality of conductive posts penetrating the first and second surfaces of the semiconductor substrate and the adhesive layer and electrically connected to the semiconductor chip, thereby effectively reducing the fabrication cost, shortening the fabrication time and improving the product reliability.