Semiconductor Package Fabrication Using Conductive Dielectric Sealant
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Solution Overview
Problem
Current semiconductor package fabrication processes face challenges in efficiently connecting integrated-circuit chips to substrates and encapsulating them in a way that ensures reliable electrical connections and effective singulation of packages.
Innovation Solution
A process involving a substrate with electrical connection pads on both faces, connected via a network, where integrated-circuit chips are mounted using a dielectric sealant containing conductive particles, and encapsulated in a block of material, followed by dicing to create individual packages, allowing for precise electrical connections and efficient encapsulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional bonding and encapsulation processes are used, then chips can be connected to substrates, but the process complexity increases and manufacturing efficiency decreases
Solution Approach 1:
The substrate is divided into multiple identical units with standardized pad configurations, allowing parallel processing and assembly. The modular design enables simultaneous mounting of multiple chips on different substrate sections, thereby increasing productivity without proportionally increasing process complexity.
Solution Approach 2:
The substrate design incorporates universal electrical connection means that can serve multiple functions: electrical connection, mechanical support, and alignment reference. This multi-functionality reduces the number of separate components and process steps needed, thereby improving manufacturing efficiency while maintaining necessary complexity.
2Reliability
If precise electrical connections are ensured through conventional methods, then reliability improves, but manufacturing precision requirements increase
Solution Approach 1:
The substrate is pre-configured with electrical connection means including pads and conductive paths before chip mounting. This preliminary preparation ensures that alignment references are already in place, reducing the precision demands during the actual chip placement operation while guaranteeing reliable electrical connections.
Solution Approach 2:
Conductive adhesive material is used as an intermediary between chip pads and substrate pads. This intermediary component provides tolerance for minor misalignments while ensuring reliable electrical connection, thereby reducing the stringency of manufacturing precision requirements without compromising connection reliability.
3Productivity
If chips are encapsulated in blocks with small numbers per block, then individual package integrity is maintained, but productivity decreases
Solution Approach 1:
The encapsulation block is designed to contain multiple semiconductor packages that are pre-segmented by dashed lines indicating future cut paths. This segmentation approach allows high-density packaging in a single encapsulation operation, improving productivity while the predefined segmentation lines ensure precise singulation during the dicing process.
4Reliability
If conductive particles are embedded in sealing layer for electrical connection, then connection reliability improves, but manufacturing complexity increases
Solution Approach 1:
The conductive adhesive material's properties are optimized by controlling particle concentration, size distribution, and material composition. By adjusting these parameters, the material achieves reliable electrical conductivity while maintaining ease of application through standard deposition techniques, thus improving connection reliability without significantly increasing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures reliable electrical connections between chips and substrates, facilitates efficient encapsulation, and enables the singulation of semiconductor packages with improved structural integrity and connectivity.
Implementation Method 1
positioning of integrated-circuit chips on said front locations respectively, flattening the sealing layer, and in positions such that the pads of these chips are selectively connected electrically to the front pads of the corresponding front locations of the substrate by means of particles of the sealing layer lying therebetween
Implementation Method 2
the periphery of this sheet being fastened to an annular frame, the sealing layer deposition, chip positioning, encapsulation and dicing operations all being carried out with the rear face of the substrate placed on a suction table
Implementation Method 3
The encapsulation may be carried out by compression molding, immersing the chips mounted on the substrate in a chamber of a mold containing a curable encapsulation material until this material encounters the front face of the substrate and/or the sealing layer
Data Source
AI summary
A substrate is provided with electrical connection pads on a front face and on a rear face, the front pads and rear pads being selectively connected via a network passing through the substrate. A peripheral edge of the substrate is mounted on a rigid annular frame and the rearm face secured to a suction table. A layer of a dielectric sealant containing electrically conductive particles is deposited on the front face and front pads of the substrate. Integrated-circuit chips are positioned on the front face to flatten the layer of dielectric sealant, the included electrically conductive particles making electrical connection between pads of the integrated-circuit and the front pads of the substrate. The resulting assembly in then encapsulated in a block of encapsulating material positioned on top of the front face of the substrate. The block is then diced in order to obtain a plurality of semiconductor packages.