Semiconductor Package Conductive Segments for High-Density Interconnects
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Solution Overview
Problem
Conventional semiconductor package structures of flip chip bonding face limitations in reducing the pitch of the redistribution layer circuit and increasing connecting positions due to the larger size of pads compared to the line width, which restricts the number of external connections.
Innovation Solution
The semiconductor package structure incorporates a die with interconnect metal layers and low k inter-level dielectrics, featuring first conductive segments exposed from the surface for external connections, and a package substrate with second conductive segments that match the pitch of the first segments, allowing for a more compact and increased number of connecting positions through optimized circuit design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If solder balls and pads are used to electrically connect die and package substrate, then reliable electrical connection is achieved, but the pitch in the redistribution layer circuit cannot be effectively reduced and the number of connecting positions is limited
Solution Approach 1:
The conductive connection structure is segmented into multiple interconnect metal layers (first, second, third interconnect metal layers) with corresponding inter-level dielectrics. This segmentation allows the redistribution layer circuit to be divided into multiple levels, enabling pitch reduction in each layer while providing multiple planes for external connections, thereby increasing the number of connecting positions without compromising reliable electrical connection.
2Reliability
If pad size is increased to ensure solder ball attachment, then reliable solder joint is achieved, but the pitch in the circuit cannot be effectively reduced
Solution Approach 1:
The connection structure transitions from a single-plane pad design to a multi-layer vertical architecture. The first, second, and third interconnect metal layers are stacked vertically with inter-level dielectrics in between, allowing the circuit to utilize the third dimension (vertical stacking). This enables smaller in-plane pitch while maintaining reliable electrical connection through the vertical stack, effectively decoupling pad size constraints from pitch reduction goals.
3Quantity of substance
If conventional flip chip bonding with solder balls is used, then electrical connection is achieved, but the number of external connections is precluded from increase
Solution Approach 1:
The interconnect structure employs a nested multi-layer configuration where the first interconnect metal layer is embedded in the first inter-level dielectric, the second interconnect metal layer is embedded in the second inter-level dielectric, and the third interconnect metal layer is exposed on the surface. Each layer is nested within the vertical stack, allowing multiple connection levels to be compactly integrated. This nested architecture increases the number of external connections without proportionally increasing device footprint or overall complexity.
Data Source
AI summary
The present disclosure relates to a semiconductor package structure, including a die and a package substrate. The die includes a semiconductor substrate, multiple interconnect metal layers, and at least one inter-level dielectric disposed between ones of the interconnect metal layers. Each inter-level dielectric is formed of a low k material. An outermost interconnect metal layer has multiple first conductive segments exposed from a surface of the inter-level dielectric. The package substrate includes a substrate body and multiple second conductive segments exposed from a surface of the substrate body. The second conductive segments are electrically connected to the first conductive segments.