Semiconductor Package Conductive Via Design for High I/O Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor device packages is to increase the high-density input and output (I/O) counts, particularly due to limitations in the double-side molding structure where components at the bottom side hinder easy expansion.
Innovation Solution
A semiconductor device package design featuring a carrier with a double-side molding structure, where conductive vias are formed by mechanical drilling, allowing for controlled length and size, including reduced width, thereby increasing I/O counts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a double-side molding structure is used, then the semiconductor package can accommodate components at both top and bottom sides, but the I/O counts cannot be easily increased due to component placement limitations
Solution Approach 1:
The patent introduces conductive vias that extend through the first encapsulant from its top surface to its bottom surface, creating a vertical dimension for electrical connections. This allows I/O signals to be routed through the encapsulant body rather than only through peripheral traces, effectively adding a third dimension (depth) to the I/O architecture and enabling higher I/O counts without increasing planar complexity
Solution Approach 2:
The encapsulant is divided into distinct regions: a first encapsulant covering the bottom surface with conductive vias extending through it, and a second encapsulant covering the top surface. This segmentation allows independent optimization of each encapsulant region, with the first encapsulant serving as a substrate for high-density via arrays while the second encapsulant provides top-side protection and component mounting support
2Adaptability or versatility
If conventional via formation methods are used, then the manufacturing process is simpler, but the via width cannot be reduced to increase I/O density
Solution Approach 1:
The patent replaces conventional chemical or photolithographic via formation methods with mechanical drilling. This mechanical approach enables precise control of via dimensions including width and depth, allowing for reduced via widths that increase I/O density while maintaining manufacturing precision through direct mechanical removal of material rather than chemical etching or photopatterning
3Adaptability or versatility
If the via width is reduced to increase I/O counts, then more I/O connections are possible, but the manufacturing precision requirements increase
Solution Approach 1:
Mechanical drilling provides direct, controllable removal of material with precise dimensional tolerances. The drill bit diameter directly determines the via width, enabling consistent, narrow via dimensions to be achieved with high precision. This mechanical approach offers better control over via width compared to chemical etching or photolithography, allowing reduced via widths for higher I/O counts while maintaining manufacturability
Solution Approach 2:
The patent changes the fundamental parameter of via formation from chemical/photon-based processes to mechanical drilling. This parameter change enables precise control of via dimensions including width, depth, and aspect ratio. The mechanical drilling process allows independent optimization of these parameters, facilitating reduced via widths for increased I/O density while maintaining manufacturing precision through direct mechanical control
Data Source
AI summary
A semiconductor device package and a method for manufacturing the semiconductor device package are provided. The semiconductor device package includes a carrier, an electronic component, a first encapsulant and a conductive via. The carrier has a first surface and a second surface opposite to the first surface. The semiconductor device is mounted at the second surface of the carrier. The first encapsulant encapsulates the first surface of the carrier and has a surface facing away from the first surface of the carrier. The conductive via extends from the surface of the first encapsulant into the carrier.