3D Stacked Semiconductor Package with Conductive Vias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor packaging technologies face limitations in creating compact, efficient, and power-effective solutions for integrating sensors and processors, particularly in reducing system size and power consumption while ensuring reliable thermal management and mechanical protection.
Innovation Solution
A three-dimensional (3D) system-in-package approach is implemented using a wafer-level process, where a first semiconductor die and a second sensor die are vertically stacked with thin redistribution structures formed by a fan-out method, and connected via conductive vias, allowing for a very thin package with reduced horizontal area and vertical thickness, and employing encapsulants with varying mechanical properties for protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional semiconductor packaging is used, then manufacturing process is simple, but system size and power consumption are reduced
Solution Approach 1:
The patent transitions from conventional two-dimensional packaging to three-dimensional stacked packaging, where sensor dies and processor dies are vertically stacked and connected via through-silicon vias (TSVs). This dimensional change enables significant reduction in horizontal footprint while maintaining functional integration, directly resolving the contradiction between reducing system size and managing packaging complexity.
Solution Approach 2:
The patent implements nested packaging where sensor dies are embedded within a substrate, and processor dies are stacked above them with interconnections formed through the substrate. Multiple functional components are nested within each other in vertical space, achieving compact integration that reduces overall system size while organizing complexity in a structured manner.
2Temperature
If conventional packaging is used, then manufacturing is straightforward, but thermal management efficiency deteriorates
Solution Approach 1:
The patent introduces thermal interface materials and thermally conductive underfills as intermediary layers between dies and substrate. These intermediary components facilitate efficient heat transfer from hot spots in the stacked dies to the substrate's thermal management structures, improving thermal management while adding targeted complexity only where needed for heat dissipation.
3Area of stationary object
If 3D stacked packaging is implemented, then horizontal area is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary formation of through-silicon vias (TSVs) and interconnection structures in the substrate before stacking the dies. Carrier substrates are used to pre-assemble and pre-align multiple dies with their interconnection structures, ensuring precise registration. This preliminary preparation simplifies the final stacking process and reduces manufacturing complexity despite the advanced 3D packaging architecture.
Data Source
AI summary
A semiconductor device includes a first semiconductor die, a first encapsulant surrounding the first semiconductor die, and a first redistribution structure formed on the first semiconductor die and the first encapsulant. The semiconductor device further includes a second semiconductor die, a second encapsulant surrounding the second semiconductor die, and a second redistribution structure formed on the second semiconductor die and the second encapsulant. The semiconductor device also include a conductive via electrically connecting the first redistribution structure to the second redistribution structure.