Semiconductor Package With Metallized Conical Vias
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Solution Overview
Problem
The high cost of lead frame and substrate materials, along with the limitations on design options and increased chemical consumption and manufacturing time due to electro-less/electroplating processes, pose challenges in producing semiconductor products, particularly for automotive-grade applications.
Innovation Solution
Replacing traditional lead frames with substrates featuring metallized conical vias created through laser ablation and electro-less plating plus electroplating, and using balls to partially fill via holes to form stud bumps, which prevent resin leakage and reduce filling time and material consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional lead frames are used, then structural support is provided, but cost increases and design flexibility decreases
Solution Approach 1:
The patent removes the traditional lead frame structure entirely and replaces it with a substrate-based architecture. The substrate alone provides the necessary structural support, while the lead frame function is achieved through metallized vias and conductive paths integrated into the substrate, thereby eliminating unnecessary complexity and increasing design flexibility.
Solution Approach 2:
The substrate serves multiple functions simultaneously: it provides mechanical support, electrical connectivity through metallized vias, and thermal management pathways. This multi-functional approach eliminates the need for separate lead frame components, reducing overall device complexity while maintaining structural integrity.
2Reliability
If electro-less/electroplating is used for via filling, then electrical conductivity is achieved, but chemical consumption increases and manufacturing time increases
Solution Approach 1:
Instead of completely filling all vias with conductive material through time-consuming electro-less/electroplating processes, the patent selectively fills only the critical vias that require electrical connectivity. Non-critical vias remain partially filled or unfilled, significantly reducing chemical consumption and manufacturing time while maintaining necessary electrical conductivity for device operation.
3Reliability
If electro-less/electroplating is used for via filling, then electrical conductivity is achieved, but chemical consumption increases
Solution Approach 1:
The patent applies via filling selectively only where electrical conductivity is absolutely necessary, rather than uniformly filling all vias. This partial action approach dramatically reduces the consumption of electro-less/electroplating chemicals while ensuring that all critical electrical pathways are properly conductive for reliable device operation.
4Reliability
If via holes are completely filled with conductive material, then electrical connectivity is ensured, but manufacturing time and material cost increase
Solution Approach 1:
The patent implements a selective via filling strategy where only the essential vias requiring electrical connectivity are completely filled with conductive material. Non-essential vias are left partially filled or unfilled, thereby maintaining necessary electrical connectivity while significantly improving manufacturing efficiency by reducing material deposition time and material costs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in lower-cost, automotive-grade semiconductor packages with reduced manufacturing time and material usage, while maintaining effective electrical and thermal conductivity, and eliminating the need for metallic frames, thus enhancing design flexibility.
Implementation Method 1
substrate with metallized (e.g., conical) vias and routing obtained through laser ablation
Implementation Method 2
electro-less plating plus electroplating
Implementation Method 3
electro-less plating plus electroplating
Data Source
AI summary
A semiconductor product such as an integrated circuit includes a laminar plastic substrate having first and second opposed surfaces and through holes extending through the substrate, electrically and/or thermally conductive material balls inserted in the through holes at the first surface of the substrate, and one or more semiconductor chips mounted at the first surface of the substrate, the semiconductor chip(s) electrically and/or thermally coupled with electrically and/or thermally conductive material balls inserted in the through holes.