Semiconductor Package Connection Layer Without Photoresist
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Solution Overview
Problem
Current semiconductor packages face challenges in reliability and miniaturization due to the complexity of electrical connections, which often require photoresist materials that can deteriorate and increase manufacturing costs.
Innovation Solution
The semiconductor package design includes a connection layer with a solder pattern and metal patterns stacked vertically, overlapping through vias, eliminating the need for a photo process and reducing the use of photoresist materials, thereby enhancing reliability and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photoresist materials and photo process are used for electrical connections, then manufacturing precision can be achieved, but reliability deteriorates due to residual photoresist materials and manufacturing costs increase
Solution Approach 1:
The patent extracts and eliminates the photoresist material and photo process from the electrical connection structure. By using a direct metal pattern and solder pattern formation process without photoresist, the harmful residual materials are completely removed, solving the reliability issue while maintaining manufacturing precision through direct patterning methods
Solution Approach 2:
The patent replaces expensive and problematic photoresist materials with a simpler, more reliable metal pattern formation process. The disposable photoresist layer that causes reliability issues is substituted with a direct metallization approach that eliminates the need for photoresist removal and cleaning steps
2Manufacturing precision
If photo process is used for electrical connections, then manufacturing precision can be achieved, but manufacturing complexity increases due to additional process steps
Solution Approach 1:
The patent extracts the photo process steps (photoresist coating, exposure, development, and removal) from the manufacturing sequence. This elimination simplifies the overall manufacturing process while maintaining electrical connection precision through alternative direct patterning methods using metal patterns and solder patterns
Solution Approach 2:
The patent merges the electrical connection formation process with the existing metal pattern and solder pattern layers. By integrating the connection structure directly into the metal pattern formation process rather than adding separate photo process steps, the manufacturing complexity is reduced while maintaining precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the reliability of semiconductor packages by preventing electrical characteristic deterioration from residual photoresist materials and reduces manufacturing costs by omitting the photo process, while allowing for more efficient electrical connections.
Implementation Method 1
a through via penetrating the first insulating layer... a lower surface of the through via is in contact with an upper surface of the solder pattern
Implementation Method 2
a connection layer disposed between the connection substrate and the lower redistribution substrate, wherein the connection layer includes a first metal pattern and a solder pattern disposed on the first metal pattern
Data Source
AI summary
A semiconductor package includes a first semiconductor package and a second semiconductor package on the first semiconductor package. The first semiconductor package includes a lower redistribution substrate, a connection substrate on the lower redistribution substrate, the connection substrate includes a through hole, a first insulating layer and a through via penetrating the first insulating layer, a lower semiconductor chip in the through hole, a connection layer between the connection substrate and the lower redistribution substrate, the connection layer includes a first metal pattern and a solder pattern on the first metal pattern, a first molding layer on the lower semiconductor chip and the connection substrate, and an upper redistribution substrate on the first molding layer. The second semiconductor package includes a package substrate, an upper semiconductor chip on the package substrate, and a second molding layer on the package substrate and the upper semiconductor chip.