Semiconductor Package Connection Pads Mitigating Thermal Stress
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Solution Overview
Problem
The reliability of semiconductor packages is compromised due to cracking in electrical connection structures, particularly at the interface between dissimilar materials, which can lead to thermal stress and propagation of defects, affecting the overall performance and durability of the package.
Innovation Solution
The semiconductor package design includes a connection member with a redistribution layer, UBM pads, and connection pads, where the connection pads are strategically expanded in size to mitigate thermal stress and prevent crack propagation, with the UBM pads located in both overlapping and non-overlapping regions with the semiconductor chip, and the pads' areas are optimized to manage thermal expansion differences effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If connection pads are expanded in size to mitigate thermal stress and prevent crack propagation, then reliability is improved, but device complexity increases
Solution Approach 1:
The connection pads are designed with non-uniform sizes based on their specific locations and functional requirements. First connection pads have larger areas than second connection pads, creating local variations in pad geometry that optimize thermal stress distribution and crack resistance at different regions of the electrical connection structure.
Solution Approach 2:
The electrical connection structure is segmented into multiple discrete connection pads with different area characteristics. This segmentation allows each pad to be independently optimized for its specific function, with first connection pads designed for high-stress regions and second connection pads for lower-stress regions, thereby managing overall structural complexity through modular design.
2Strength
If connection pads are expanded in size to block crack propagation, then strength is improved, but manufacturing precision requirements increase
Solution Approach 1:
Different connection pads are assigned different area specifications based on their location and stress requirements. First connection pads have larger areas for enhanced strength and crack blocking in critical regions, while second connection pads have smaller areas for regions with lower stress demands, allowing manufacturing processes to target precision requirements to specific pad types rather than requiring uniform high precision across all pads.
Solution Approach 2:
The design specifies distinct area parameters for different connection pad types (first connection pads with larger areas, second connection pads with smaller areas). This parameter differentiation allows manufacturing processes to use appropriate tolerance ranges for each pad type, reducing overall manufacturing precision requirements compared to requiring all pads to meet a single high-precision specification.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the thermal reliability of the semiconductor package by blocking crack propagation and improving the structural integrity of the electrical connection structures, thereby increasing the package's reliability and durability.
Implementation Method 1
the pads' areas are optimized to manage thermal expansion differences effectively
Data Source
AI summary
A semiconductor package includes: a connection member including a plurality of connection pads and a redistribution layer; a semiconductor chip disposed on the connection member; an encapsulant sealing the semiconductor chip; a passivation layer disposed on the connection member; a plurality of under bump metallurgy (UBM) pads disposed on the passivation layer; and a plurality of UBM vias connecting the plurality of UBM pads to the plurality of connection pads, respectively, wherein the plurality of UBM pads include a first UBM pad overlapped with the semiconductor chip in a stacking direction, and a second UBM pad located outside of the overlapped region, and the first connection pad has an area larger than an area of an associated first UBM pad while the associated first UBM pad is overlapped in the stacking direction, and has an area larger than an area of the second connection pad.