Multi-Layer Semiconductor Package Contacts Layout

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Solution Overview

Problem

The increasing complexity of semiconductor circuits and the number of signal pins poses difficulties during circuit layout for package substrates in existing semiconductor package structures, such as ball grid array packages, due to overcrowding and spacing challenges.

Innovation Solution

A semiconductor package structure with first-layer, second-layer, third-layer, and fourth-layer electrical contacts arranged sequentially on the bottom surface, featuring alternating spacings between adjacent contacts, with a first spacing and a second spacing twice the first spacing, facilitating easier circuit layout by allowing conductors to pass through larger gaps, thereby reducing congestion and layout difficulties.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of signal pins is increased to meet circuit complexity requirements, then the transmission capacity is improved, but the circuit layout difficulty increases due to overcrowding

Engineering Contradiction:
Improvenumber of signal pinsVSAvoidcircuit layout difficulty
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The electrical contacts are divided into four distinct layers arranged sequentially from outside to inside on the bottom surface. This segmentation allows signals to be distributed across multiple layers, reducing overcrowding on any single layer and simplifying circuit layout while maintaining high transmission capacity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a conventional two-dimensional array of electrical contacts to a three-dimensional multi-layer structure. By arranging electrical contacts in four sequential layers, the patent utilizes the vertical dimension to increase the number of signal pins without increasing the planar footprint, thereby avoiding layout overcrowding.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If uniform spacing is used between adjacent electrical contacts, then the manufacturing process is simplified, but the circuit layout flexibility is reduced

Engineering Contradiction:
Improvespacing uniformityVSAvoidcircuit layout flexibility
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent implements non-uniform spacing between adjacent electrical contacts within the same layer, creating different local spacing characteristics. This allows certain regions to have tighter spacing for high-density connections while other regions have wider spacing for easier routing, thereby improving circuit layout flexibility without compromising manufacturing feasibility.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11710713B2Semi-conductor package structure
Publication Date: 2023.07.25 INTEL CORP
  • US11710713B2 patent drawing
  • US11710713B2 patent drawing
  • US11710713B2 patent drawing

AI summary

Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts, wherein the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts are arranged sequentially from outside to inside on a bottom surface of the body in a matrix manner. Adjacent first-layer electrical contacts have two different spacings therein, and adjacent third-layer electrical contacts have the two different spacings therein.