Semiconductor Package Layout for Contrast Ratio and Current Spreading
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Solution Overview
Problem
Semiconductor devices with multiple chips face issues of optical interference and difficulty in improving contrast ratio due to close spacing, especially when independently controlling each chip.
Innovation Solution
A semiconductor device package design with a specific height-to-separation ratio of semiconductor structures, channel layers, and interconnection lines to enhance current spreading and contrast ratio, featuring a substrate with spaced semiconductor structures, interconnection lines, and electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a plurality of chips are disposed close to each other to appear as one light source, then the visual integration is improved, but optical interference occurs and contrast ratio deteriorates
Solution Approach 1:
The patent introduces an intermediate layer between adjacent semiconductor structures that selectively blocks light propagation paths. This intermediary layer prevents optical interference between closely-spaced chips while allowing each chip to function independently, thereby maintaining visual integration without suffering from optical interference effects.
Solution Approach 2:
The patent applies different properties to different regions by creating localized light blocking structures between specific adjacent chips. The intermediate layer is positioned only where optical interference occurs, allowing light to pass in regions where it is needed while blocking it in regions where interference problems arise, thus achieving local optimization of light control.
2Productivity
If multiple semiconductor structures are closely spaced, then the device integration is improved, but current spreading becomes difficult
Solution Approach 1:
The patent addresses current spreading issues by introducing vertical dimensionality through multi-layer interconnection structures. Instead of relying solely on lateral current distribution in a single plane, the design uses stacked conductive layers and vertical vias to distribute current across multiple dimensions, enabling effective current spreading even when chips are closely spaced horizontally.
3Adaptability or versatility
If independent control of each chip is implemented, then the functionality is improved, but contrast ratio improvement becomes difficult
Solution Approach 1:
The intermediate layer serves as a spatial mediator that enables independent control of each semiconductor structure by blocking light from adjacent structures. This allows each chip to be controlled independently while maintaining high contrast ratio, as the light blocking prevents crosstalk between independently controlled chips.
Data Source
AI summary
A semiconductor device package includes a substrate; and a plurality of semiconductor structures disposed to be spaced apart from each other at a central portion of the substrate. Further, the semiconductor structure is disposed on the substrate and includes a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer disposed on the first conductivity-type semiconductor layer, and an active layer disposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer. The semiconductor device package also includes a plurality of first interconnection lines disposed between the substrate and the plurality of semiconductor structures and electrically connected to the first conductivity-type semiconductor layer; and a plurality of second interconnection lines disposed between the substrate and the plurality of semiconductor structures and electrically connected to the second conductivity-type semiconductor layer.