Semiconductor Package Coplanar Bonding With Planarization Layer
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Solution Overview
Problem
Existing semiconductor device packages face challenges in achieving coplanarity during bonding due to uneven surfaces of carriers and semiconductor devices, leading to potential reliability and performance issues.
Innovation Solution
A semiconductor device package design featuring a carrier with a planarization layer on an uneven surface, where the planarization layer is conformal to the carrier's surface and has conductive elements with controlled elevation, ensuring coplanarity between the carrier and semiconductor devices, and using a holder to precisely position and bond the devices with minimal lateral signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a planarization layer is added to achieve coplanarity, then bonding reliability is improved, but device complexity increases
Solution Approach 1:
A planarization layer is introduced as an intermediary component between the carrier and the semiconductor device. This planarization layer fills in the uneven surfaces of the carrier, creating a coplanar bonding surface that ensures reliable bonding while the holder provides mechanical support and positioning during the bonding process
2Ease of manufacture
If the carrier surface is made uneven for component mounting, then manufacturing flexibility is improved, but bonding coplanarity deteriorates
Solution Approach 1:
The uneven surface of the carrier is prepared in advance to accommodate various components with different mounting requirements. The planarization layer is then applied as a preliminary action before bonding to create a coplanar surface, allowing both manufacturing flexibility and bonding precision to be achieved
3Adaptability or versatility
If conductive elements are positioned at different elevations, then routing flexibility is improved, but signal transmission performance deteriorates
Solution Approach 1:
The holder is designed to position conductive elements at substantially the same elevation, creating an equipotential bonding surface. This ensures optimal signal transmission performance by minimizing impedance variations while still allowing routing flexibility through the planarization layer's conformal structure
Data Source
AI summary
A semiconductor device package includes a carrier provided with a first conductive element, a second conductive element arranged on a semiconductor disposed on the carrier, and a second semiconductor device disposed on and across the first conductive element and the first semiconductor device, wherein the first conductive element having a surface that is substantially coplanar with a surface of the second conductive element.