Semiconductor Package Routing With Small Core Vias
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Solution Overview
Problem
The existing 2.5D semiconductor packages require a large number of conductive layers due to the mismatch in diameters between core vias and bumps, leading to complex signal transmission paths and increased package size, which complicates signal routing and integrity.
Innovation Solution
A semiconductor package design with a substrate that includes a core layer capable of forming small-diameter core vias and a redistribution structure, allowing vertical signal wires to penetrate through the substrate, reducing the number of conductive layers and improving signal integrity by securing spacing between neighboring vertical signal wires using redistribution lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large number of conductive layers are used to accommodate signal routing requirements, then signal transmission paths can be established, but the substrate complexity and package size increase
Solution Approach 1:
The patent transitions from purely horizontal signal routing in the core layer to vertical signal transmission through the core layer using small-diameter core vias. This dimensional change allows signals to pass directly through the core layer to the lower stacking structure, eliminating the need for multiple horizontal routing layers and reducing overall substrate complexity while maintaining reliable signal transmission.
2Ease of manufacture
If the core via diameter is made large to match bump diameter, then manufacturing is easier, but the layout cannot overlap and signals cannot be transmitted directly vertically
Solution Approach 1:
The patent changes the diameter parameter of core vias from large (matching bump diameter) to small (independent dimension). This parameter change enables the core via layout to overlap with the bump layout, allowing direct vertical signal transmission from bumps through the core layer to the lower stacking structure, thereby simplifying signal routing complexity while maintaining ease of manufacture through standardized small via fabrication processes.
3Ease of operation
If signals are routed horizontally through the core layer, then connection is achieved, but the number of conductive layers increases to 12-14 layers
Solution Approach 1:
The patent introduces vertical signal paths through the core layer using small-diameter core vias, changing the routing dimension from horizontal to vertical. This allows signals to be transmitted directly from the top surface through the core layer to the lower stacking structure, eliminating the need for multiple horizontal routing layers and reducing the total conductive layer count from 12-14 layers to a minimal configuration.
4Device complexity
If vertical signal wires are formed through the core layer, then the number of conductive layers is reduced, but spacing between neighboring wires must be precisely controlled to avoid insertion loss and return loss
Solution Approach 1:
The patent precisely controls the spacing parameter of vertical signal wires formed through small-diameter core vias. By optimizing the pitch and spacing of these vias during the design stage, the patent achieves proper impedance matching and minimizes insertion loss and return loss, thereby maintaining signal integrity while reducing the number of conductive layers.
Data Source
AI summary
A semiconductor package according to an embodiment includes a substrate including a first signal layer, a core layer on the first signal layer, and a second signal layer on the core layer; a redistribution structure disposed on the substrate and including a plurality of redistribution lines; and a semiconductor die on the redistribution structure. A signal transmitted to or from the semiconductor die is routed through a first horizontal path within the first signal layer; a first vertical path extending from the first signal layer to a corresponding redistribution line among the plurality of redistribution lines; a second horizontal path within the corresponding redistribution line; and a second vertical path extending from the corresponding redistribution line to the semiconductor die.