Semiconductor Package Barrier Structure for Adhesive Crack Blocking

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Solution Overview

Problem

The reliability of semiconductor packages is compromised by the occurrence of cracks in the region between stacked semiconductor chips due to stress concentration in the adhesive layer, which can propagate to the interconnection layers.

Innovation Solution

A barrier structure is introduced to cover the connection pads and protruding portions of the adhesive layer, preventing crack propagation from the adhesive layer to the underlying interconnection layers by spacing apart from the connection bumps and extending around the regions where the bumps are disposed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If connection bumps are used to electrically connect stacked semiconductor chips, then electrical connectivity between chips is achieved, but stress concentration occurs in the adhesive layer which can cause cracks to propagate to interconnection layers

Engineering Contradiction:
Improvereliability of semiconductor packageVSAvoidcrack propagation in adhesive layer
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A barrier structure is introduced as an intermediary element between the adhesive layer and the connection pads/interconnection layers. This barrier structure prevents direct stress transmission and crack propagation from the adhesive layer to the sensitive interconnection layers, while still allowing the connection bumps to maintain electrical connectivity between stacked semiconductor chips.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The barrier structure is positioned in advance to cushion and absorb the stress concentration that occurs in the adhesive layer during package assembly and operation. By having this protective structure in place before cracks can form or propagate, the interconnection layers are protected from damage that would otherwise occur under normal operating conditions.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Strength

If adhesive layer completely surrounds connection bumps, then mechanical bonding between chips is achieved, but stress concentration in the adhesive layer can propagate cracks to interconnection layers

Engineering Contradiction:
Improvemechanical bonding strengthVSAvoidstress concentration and crack propagation
Core Design Contradiction:
StrengthVSObject-affected harmful factors

Solution Approach 1:

The protective barrier structure is segmented to selectively cover only the connection pads and interconnection layers that are at risk from crack propagation, while leaving the connection bumps and adhesive layer intact to maintain mechanical bonding. This segmented approach allows the adhesive layer to provide full mechanical support while the barrier structure provides targeted protection against crack propagation.

Inventive Principle:
Principle #1Segmentation

3Object-affected harmful factors

If barrier structure covers connection pads and protruding adhesive layer, then crack propagation is prevented, but device structure becomes more complex

Engineering Contradiction:
Improvecrack propagation preventionVSAvoidstructure complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The barrier structure is applied locally only where needed - specifically covering the connection pads and protruding portions of the adhesive layer that are most susceptible to crack propagation. This local quality approach provides effective crack prevention without requiring a complete redesign of the entire package structure, thus minimizing the increase in device complexity.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12538803B2Semiconductor package including a barrier structure covering connection pads and contacting a protruding portion of an adhesive layer
Publication Date: 2026.01.27 SAMSUNG ELECTRONICS CO LTD
  • US12538803B2 patent drawing
  • US12538803B2 patent drawing
  • US12538803B2 patent drawing

AI summary

A semiconductor package includes a first semiconductor chip having a first surface and a second surface. First connection pads are adjacent to the first surface. A second semiconductor chip has a lower surface facing the first surface of the first semiconductor chip and includes second connection pads, Connection bumps contact the first connection pads and the second connection pads between the first semiconductor chip and the second semiconductor chip. An adhesive layer is interposed between the first semiconductor chip and the second semiconductor chip to at least partially surround the connection bumps. The adhesive layer includes a protruding portion protruding from a side surface of the second semiconductor chip. A barrier structure covers a portion of the first connection pads, partially overlapping the second semiconductor chip on the first surface, and contacting the protruding portion of the adhesive layer.