Offset-Stacked Semiconductor Package Support for Crack Prevention
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Solution Overview
Problem
The miniaturization of semiconductor packages leads to frequent defects in chip stacked structures due to instability and concentration of load and moment at the edges of the base chips, which can result in cracking.
Innovation Solution
A semiconductor package design that includes a support structure to stabilize the chip stacked structure by supporting the lower surface of specific base chips, dispersing the load and offsetting moments applied to the base chips, thereby preventing cracks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the size of semiconductor chips is decreased to achieve miniaturization, then the volume and weight of the semiconductor package are reduced, but the stability of the chip stacked structure deteriorates and defects frequently occur
Solution Approach 1:
A support chip is introduced as an intermediary element between the base chip and the stacked chips. This support chip receives and distributes the load from the stacked chips to a broader area of the base chip, preventing stress concentration at the edges. The support chip acts as a mediator that resolves the conflict between miniaturization and structural stability by providing additional load distribution capability without increasing the overall package volume significantly.
Solution Approach 2:
The support chip extends the load distribution in the horizontal plane (another dimension) rather than simply increasing vertical stacking height. By distributing weight across a larger surface area of the base chip through the support chip, the structure gains stability without proportionally increasing the package volume, thus addressing the contradiction between miniaturization and reliability.
2Productivity
If chips are offset-stacked to increase integration capacity, then the data processing capability is improved, but the concentration of load and moment at the edges of base chips increases causing cracks
Solution Approach 1:
The support chip serves as a mediator that intercepts the concentrated load and moment forces generated by offset-stacked chips before they reach the vulnerable edges of the base chip. By positioning the support chip to receive these forces and distribute them across a larger area, the base chip's strength is preserved while maintaining the high integration capacity provided by offset stacking.
3Productivity
If multiple chip stacked structures are mounted on a package substrate, then the integration capacity and data processing capability are improved, but the complexity of the package structure increases
Solution Approach 1:
The package structure is segmented into distinct functional modules: base chips, support chips, and stacked chips. Each support chip is independently positioned to provide localized reinforcement for specific stacked structures. This segmentation allows the complexity to be managed in distributed units rather than requiring a monolithic complex structure, enabling high integration capacity while keeping individual structural elements relatively simple.
Data Source
AI summary
Provided is a semiconductor package including a package substrate including a substrate pad, a first chip stacked structure including a first base chip mounted on an upper surface of the package substrate, and one or more first stacked chips sequentially offset-stacked along a first direction on the first base chip, a second chip stacked structure including a second base chip offset-stacked along the first direction on an upper surface of the first chip stacked structure, and one or more second stacked chips sequentially offset-stacked along the first direction on the second base chip, a bonding wire, and a first support mounted on the package substrate to be spaced apart from the first chip stacked structure in the first direction and supporting the second chip stacked structure, wherein the first support supports the second chip stacked structure by supporting a lower surface of the second base chip.