Power Semiconductor Package Pin Layout for Creepage Isolation
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Solution Overview
Problem
Packaged power semiconductor devices face challenges in miniaturization due to pin creepage phenomena in high voltage environments, which compromise safety and reliability.
Innovation Solution
A packaged power semiconductor device design that includes a power semiconductor wafer, heat conduction layer, and heat sink, sealed by a sealing part, with a pin configuration that ensures a minimum distance between the exposed extension segment and the heat sink surface exceeds the creepage distance based on the device's working voltage, incorporating insulation and heat dissipation layers to prevent creepage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the integration degree of components is improved to achieve miniaturization, then the size of the packaged power semiconductor device is reduced, but the pin creepage phenomenon occurs more easily in high voltage environments
Solution Approach 1:
The patent extends the pin structure in the vertical dimension by adding an extension segment that protrudes from the sealing part. This dimensional extension allows the pin to maintain adequate creepage distance from the heat sink surface while keeping the overall device footprint compact, thereby resolving the contradiction between miniaturization and creepage resistance.
Solution Approach 2:
The pin is segmented into two distinct parts: a connection segment inside the sealing part for electrical connection, and an extension segment outside the sealing part for maintaining creepage distance. This segmentation allows each part to fulfill its specific function independently, enabling miniaturization while preventing creepage phenomena.
2Reliability
If the distance between the pin and heat sink is increased to prevent creepage, then the safety and reliability are improved, but the device size increases
Solution Approach 1:
Instead of increasing the horizontal distance between pin and heat sink (which would increase device footprint), the patent utilizes the vertical dimension by extending the pin upward from the sealing part. This allows adequate creepage clearance to be achieved without proportionally increasing the overall device volume, thus resolving the contradiction between safety and miniaturization.
3Ease of operation
If the pin is exposed outside the sealing part for external connection, then the electrical connection function is achieved, but the pin becomes vulnerable to creepage phenomena
Solution Approach 1:
The pin is divided into a connection segment (inside sealing part) that provides electrical connection functionality and an extension segment (outside sealing part) that provides creepage protection. The connection segment remains protected within the sealing part while the extension segment extends outward to maintain safe distance from the heat sink, thus achieving both electrical connectivity and creepage resistance.
Solution Approach 2:
The extension segment acts as an intermediary structure between the protected connection segment and the external environment. It extends the electrical connection capability to the outside while maintaining the protective barrier of the sealing part, and simultaneously ensures adequate creepage distance from the heat sink surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves miniaturization while enhancing safety and reliability by preventing pin creepage and ensuring effective heat dissipation and electrical isolation, thereby improving the performance and durability of the device.
Implementation Method 1
a heat conduction layer, including an upper heat conduction layer, an insulation layer, and a lower heat conduction layer that are stacked, where the insulation layer is located between the upper heat conduction layer and the lower heat conduction layer, and the upper heat conduction layer is bonded to the power semiconductor wafer; a heat sink, including a first outer surface, where the first outer surface is bonded to the lower heat conduction layer
Implementation Method 2
an insulation layer, and a lower heat conduction layer that are stacked, where the insulation layer is located between the upper heat conduction layer and the lower heat conduction layer
Implementation Method 3
a sealing part, configured to wrap and seal the power semiconductor wafer and at least part of the heat conduction layer; and a pin, including a connection segment and an extension segment, where the connection segment is electrically connected to the power semiconductor wafer and is also wrapped in the sealing part, the extension segment is located outside the sealing part, and a shortest distance between the extension segment and the first outer surface is greater than a creepage distance corresponding to a highest working voltage of the power semiconductor wafer
Data Source
AI summary
A packaged power semiconductor device includes a power semiconductor wafer, a heat conduction layer, and a heat sink that are sequentially stacked, and a sealing part configured to wrap and seal the power semiconductor wafer and at least part of the heat conduction layer. The packaged power semiconductor device further includes a pin, where the pin includes a connection segment wrapped inside the sealing part, and an extension segment located outside the sealing part. The connection segment is electrically connected to the power semiconductor wafer, and a shortest distance between the extension segment and a first outer surface is greater than a creepage distance corresponding to a highest working voltage of the power semiconductor wafer. This can avoid a creepage phenomenon of the pin by limiting a distance between the first outer surface and the extension segment that is of the pin and that is exposed outside the sealing part.