Semiconductor Package Anchoring Structure for CTE Mismatch Delamination
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Solution Overview
Problem
Conventional semiconductor package structures face delamination issues due to coefficient of thermal expansion (CTE) mismatch between the encapsulant and the circuit pattern structure during thermal processes, affecting reliability and performance.
Innovation Solution
Incorporating an anchoring or interlocking structure between the encapsulant and the circuit pattern structure to reduce the difference in thermal expansion variations, thereby preventing delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an encapsulant with different material properties is used to cover the circuit pattern structure, then protection and encapsulation are achieved, but delamination occurs during thermal processes due to CTE mismatch
Solution Approach 1:
The patent divides the bonding interface into multiple segments by introducing a pile structure that creates multiple bonding areas between the encapsulant and circuit pattern structure. This segmentation distributes the thermal stress across multiple bonding zones, preventing delamination while maintaining overall structural integrity.
Solution Approach 2:
The patent applies local quality by creating a pile structure with specific geometric features (protrusions and recesses) at the bonding interface between the encapsulant and circuit pattern structure. This localized structural modification enhances bonding reliability at critical thermal stress points without affecting the overall device complexity significantly.
2Reliability
If a protection structure with different CTE is used to cover the top layer, then encapsulation is achieved, but delamination occurs during thermal processes
Solution Approach 1:
The patent implements beforehand cushioning by pre-forming a pile structure at the bonding interface before thermal processes occur. This pile structure acts as a cushioning element that absorbs and distributes thermal stress during subsequent thermal cycling, preventing delamination and maintaining interface stability.
Solution Approach 2:
The patent changes the physical parameters of the bonding interface by introducing a pile structure with specific geometric characteristics (height, width, spacing of protrusions). This parameter modification alters the mechanical and thermal properties of the bonding interface, enabling it to withstand thermal stress without delamination.
3Adaptability or versatility
If the encapsulant and circuit pattern structure have different materials, then functional requirements are met, but CTE mismatch causes delamination
Solution Approach 1:
The patent introduces a pile structure as an intermediary element between the encapsulant and circuit pattern structure. This intermediary structure mediates the interface between materials with different CTE, distributing thermal stress and preventing delamination while allowing the use of functionally compatible but materially different encapsulant and substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces delamination between the encapsulant and the circuit pattern structure, enhancing the reliability and performance of semiconductor package structures by mitigating CTE mismatch-induced thermal stress.
Implementation Method 1
configured to reduce a difference between a variation of expansion of the encapsulant and a variation of expansion of the circuit pattern structure in an environment of temperature variation
Data Source
AI summary
A semiconductor package structure includes a circuit pattern structure, an encapsulant and an anchoring structure. The encapsulant is disposed on the circuit pattern structure. The anchoring structure is disposed adjacent to an interface between the encapsulant and the circuit pattern structure, and is configured to reduce a difference between a variation of expansion of the encapsulant and a variation of expansion of the circuit pattern structure in an environment of temperature variation.