Semiconductor Package Molding Layers for Thermal Expansion Matching

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Solution Overview

Problem

Semiconductor packages face challenges in achieving high integration density, low power consumption, and reliability due to differences in thermal expansion characteristics among components, leading to manufacturing defects and reduced yield.

Innovation Solution

A semiconductor package design featuring a first molding layer with a high filler content for structural support and a second molding layer with a lower filler content for reduced thermal expansion, minimizing CTE differences and enhancing reliability, while maintaining desired layer heights.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If a single molding layer with high filler content is used, then structural support is improved, but thermal expansion differences cause reliability issues

Engineering Contradiction:
Improvestructural supportVSAvoidthermal expansion compatibility
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The molding compound is divided into two distinct layers: a first molding layer with high filler content (60-80 wt%) for structural support, and a second molding layer with lower filler content (30-50 wt%) for thermal expansion compatibility. This segmentation allows each layer to independently optimize its properties without compromising the other.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the molding compound are assigned different filler contents based on their functional requirements. The first molding layer surrounding the semiconductor chip uses high filler content for mechanical strength, while the second molding layer filling the gap uses lower filler content to match thermal expansion characteristics, creating local quality variations throughout the structure.

Inventive Principle:
Principle #3Local quality

2Strength

If filler content is increased to improve structural support, then manufacturing precision deteriorates due to manufacturing defects

Engineering Contradiction:
Improvestructural supportVSAvoiddefect rate
Core Design Contradiction:
StrengthVSManufacturing precision

Solution Approach 1:

The molding process is segmented into two stages with different filler contents. The first layer with high filler content provides structural integrity, while the second layer with lower filler content reduces manufacturing defects and improves filling precision, thereby resolving the contradiction between strength and manufacturing precision.

Inventive Principle:
Principle #1Segmentation

3Device complexity

If a single molding layer is used, then device complexity is reduced, but thermal expansion differences lead to reliability issues

Engineering Contradiction:
Improvemolding layer structureVSAvoidthermal expansion compatibility
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The molding compound exhibits local quality variations with different filler contents in different layers. The first molding layer has high filler content for structural support, while the second molding layer has lower filler content for thermal expansion compatibility, allowing the device to achieve reliability without excessive complexity.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design minimizes thermal expansion differences between components, reducing manufacturing defects and improving the overall reliability and productivity of semiconductor packages.

Implementation Method 1

wherein a coefficient of thermal expansion (CTE) of the second molding layer is smaller than that of the first molding layer

Methodology Applied
Scientific EffectCoefficient of thermal expansion (CTE): Thermal Expansion

Data Source

PatentUS11894403B2Semiconductor package and method for fabricating same
Publication Date: 2024.02.06 SAMSUNG ELECTRONICS CO LTD
  • US11894403B2 patent drawing
  • US11894403B2 patent drawing
  • US11894403B2 patent drawing

AI summary

A semiconductor package including a semiconductor chip on a package substrate, a transparent substrate on the semiconductor chip, an attachment dam between the semiconductor chip and the transparent substrate, the attachment dam extending along an edge of the semiconductor chip, a first molding layer on the package substrate and surrounding a side surface of the semiconductor chip and including a first epoxy resin, and a second molding layer on the package substrate and filling a space between the semiconductor chip and the first molding layer and including a second epoxy resin. The first epoxy resin includes a first filler containing at least one of silica or alumina. The second epoxy resin includes a second filler containing at least one of silica or alumina. The content of the second filler in the second epoxy resin is greater than a content of the first filler in the first epoxy resin.