Semiconductor Package Wiring Layout Without Cu Posts
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Solution Overview
Problem
In Fan Out Wafer Level Package (FOWLP) technology, the increasing height of conductive structures complicates fabrication, increases package size and manufacturing cost, and hinders effective heat dissipation due to contamination issues, limiting the use of exposed Si chip structures for heat dissipation.
Innovation Solution
A semiconductor package design featuring a first and second redistribution wiring layer with bonding wirings that connect the layers without a conductive structure, allowing for a thin profile package structure, simplified manufacturing, and effective heat emission by eliminating space restrictions and solder ball joints, while maintaining high-density interconnection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conductive structure (Cu Post) is used to connect lower and upper redistribution wiring layers, then electrical connection is achieved, but fabrication difficulty increases, package size increases, and manufacturing cost increases
Solution Approach 1:
The patent removes the Cu post conductive structure from the package design. Instead of using a vertical Cu post to connect the lower and upper redistribution wiring layers, the invention uses bonding wirings that extend from the peripheral region of the lower surface of the upper redistribution wiring layer to the lower redistribution connection pads, thereby eliminating the problematic Cu post structure while maintaining electrical connection functionality
Solution Approach 2:
The patent transitions from a vertical three-dimensional connection structure (Cu post extending upward from the lower redistribution wiring layer) to a more planar two-dimensional arrangement where bonding wirings traverse horizontally across the peripheral region. This dimensional change simplifies the overall package structure and reduces fabrication complexity
2Reliability
If the height of the conductive structure is increased, then electrical connection between layers is improved, but the number of input/output terminals decreases and manufacturing cost increases
Solution Approach 1:
The bonding wirings are positioned in the peripheral region of the lower surface of the upper redistribution wiring layer, utilizing the peripheral space rather than occupying central vertical space. This allows the bonding wirings to connect layers without interfering with the placement of multiple input/output terminals, thereby maintaining high terminal density while achieving reliable electrical connection
3Reliability
If a conductive structure (Cu Post) is used for connection, then electrical connectivity is achieved, but heat dissipation capability decreases due to contamination issues
Solution Approach 1:
The patent removes the Cu post structure that causes contamination and heat dissipation problems. The bonding wirings provide an alternative connection path that does not create the same contamination issues, thereby restoring the ability to use exposed Si chip structures for effective heat dissipation
Solution Approach 2:
The bonding wirings serve as an intermediary connection element that replaces the problematic Cu post. These wirings provide the necessary electrical connection between layers without creating contamination issues, thereby enabling effective heat dissipation through exposed Si chip structures while maintaining electrical connectivity
4Ease of manufacture
If bonding wirings are used instead of Cu post, then manufacturing cost is reduced and heat dissipation is improved, but electrical connection reliability may be compromised
Solution Approach 1:
The bonding wirings are configured to extend from the peripheral region of the lower surface of the upper redistribution wiring layer to the lower redistribution connection pads. This peripheral positioning and extended path configuration ensures reliable electrical connection while simplifying the overall structure and reducing manufacturing cost
Data Source
AI summary
A semiconductor package includes a first redistribution wiring layer, a first semiconductor device on an upper surface of the first redistribution wiring layer, a first sealing member on the first semiconductor device, a second redistribution wiring layer on the first sealing member such that a peripheral region of a lower surface of the second redistribution wiring layer is free of the first sealing member, at least one second semiconductor device on an upper surface of the second redistribution wiring layer, and a plurality of bonding wirings electrically connecting first redistribution connection pads on a lower surface of the first redistribution wiring layer and second redistribution connection pads on the peripheral region of the lower surface of the second redistribution wiring layer.