Semiconductor Package with High-Modulus Dielectric for Delamination Control
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Solution Overview
Problem
The challenge of integrating multiple semiconductor devices in a single package while achieving miniaturization, higher speed, and better electrical performance has not been adequately addressed in existing technologies, particularly in the context of wafer-level packaging.
Innovation Solution
A semiconductor package manufacturing process that includes forming semiconductor dies on a carrier with encapsulation, followed by the formation of a high-modulus dielectric layer and a redistribution structure with extension pads and conductive traces to enhance electrical connectivity and mechanical stability, using materials like copper and polyimide for conductive layers and dielectric materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor devices are integrated in a single package, then device functionality and performance are improved, but manufacturing complexity and assembly difficulty increase
Solution Approach 1:
The semiconductor package is divided into multiple functional layers including substrate, encapsulant, redistribution structure with multiple dielectric layers, and individual semiconductor dies. Each layer performs specific functions and can be manufactured independently before assembly, simplifying the overall manufacturing process while achieving multi-device integration
Solution Approach 2:
Multiple semiconductor dies are stacked vertically within the encapsulant structure, with redistribution layers nested between dies to provide electrical connections. This nested arrangement allows multiple devices to be integrated in a compact three-dimensional configuration, increasing functionality while controlling package footprint
2Volume of moving object
If miniaturization is achieved, then device size is reduced, but manufacturing precision and assembly difficulty increase
Solution Approach 1:
The package structure transitions from two-dimensional lateral arrangement to three-dimensional vertical stacking, with semiconductor dies arranged in multiple layers connected by vertical redistribution vias. This dimensional change reduces the horizontal footprint while managing complexity through vertical integration
Solution Approach 2:
Different regions of the package utilize different interconnection approaches: wire bonds for certain connections, micro-bumps for others, and through-silicon vias for vertical connections. Each interconnection method is optimized for its specific location and function, improving overall reliability while managing manufacturing complexity
3Reliability
If higher speed and better electrical performance are achieved, then transmission loss is reduced, but device complexity and power consumption increase
Solution Approach 1:
Redistribution structures with multiple dielectric layers and conductive traces are introduced as intermediary elements between semiconductor dies and external connections. These intermediaries provide optimized signal pathways with controlled impedance, reducing transmission loss and improving electrical performance while isolating the complex interconnection logic from the device design
Solution Approach 2:
Signal transmission transitions from planar routing to three-dimensional pathways through vertical vias and stacked redistribution layers. This dimensional change shortens signal paths and reduces parasitic effects, improving speed and electrical performance while consolidating multiple connection functions in the vertical dimension
Data Source
AI summary
A semiconductor package includes a first semiconductor die, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The first semiconductor die includes a conductive post in a protective layer. The encapsulant encapsulates the first semiconductor die, wherein the encapsulant is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the protective layer, wherein the high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer, wherein the redistribution structure includes a redistribution dielectric layer, and the redistribution dielectric layer is made of a third material. The protective layer is made of a fourth material, and a ratio of a Young's modulus of the second material to a Young's modulus of the fourth material is at least 1.5.