Semiconductor Package Redistribution Structure for Dense I/O Reliability
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Solution Overview
Problem
The challenge in the semiconductor industry is to develop semiconductor packages that reduce size and weight while maintaining connection reliability, particularly for highly integrated semiconductor chips with a large number of input/output terminals, where existing fan-out packages struggle with interference due to close proximity of connection terminals.
Innovation Solution
A method and structure for a semiconductor package involving a redistribution structure with conductive pillars and insulating material layers, where a first semiconductor chip is bonded to a metal pad using a solder reflow process, surrounded by a molding layer, and connected via a redistribution structure that includes redistribution lines and vias, ensuring accurate alignment and preventing electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fan-out semiconductor packages are used to reduce interference between connection terminals, then connection reliability is improved, but the distance between connection terminals increases causing larger package size
Solution Approach 1:
The patent introduces a redistribution structure with multiple layers (redistribution insulating layers, redistribution lines, and redistribution vias) to route signals in three dimensions. This allows connection terminals to be densely packed on the chip surface while maintaining electrical separation through vertical layering, thus improving connection reliability without increasing package footprint.
Solution Approach 2:
The patent employs an insulating material layer surrounding the sidewalls of conductive pillars as an intermediary structure. This insulating layer prevents direct electrical contact between adjacent conductive pillars, eliminating interference while allowing them to be positioned close together, thereby maintaining small package size while ensuring connection reliability.
2Area of stationary object
If connection terminals are placed closer together to reduce package size, then package area is reduced, but interference between connection terminals increases
Solution Approach 1:
The patent uses vertical stacking of redistribution layers to separate signal paths spatially. By routing signals through multiple vertical layers with insulating material between them, the design achieves electrical isolation without requiring large horizontal distances, thus preventing interference while maintaining compact package size.
Solution Approach 2:
The insulating material layer acts as a mediator between adjacent conductive pillars, providing electrical isolation that prevents interference. This allows connection terminals to be placed close together on the chip surface while the insulating layer ensures no harmful electrical interaction occurs between them.
3Productivity
If highly integrated semiconductor chips with increased number of I/O terminals are used, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the complex interconnection structure into modular segments: conductive pillars, insulating material layers, redistribution insulating layers, and redistribution lines. Each layer is formed through standardized photolithography and etching processes, making the manufacturing of high-density interconnections systematic and controllable despite the increased number of I/O terminals.
Solution Approach 2:
The insulating material layer is formed surrounding the sidewalls of conductive pillars before the redistribution structure is completed. This preliminary action ensures proper electrical isolation is established early in the manufacturing process, simplifying subsequent steps and enabling high integration density without proportionally increasing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and manufacturing efficiency of semiconductor packages by reducing terminal interference, improving alignment accuracy, and preventing electrical shorts, thereby enabling smaller and lighter packages with increased integration density.
Implementation Method 1
bonding the conductive pillar to the metal pad by performing a solder reflow process by using a connection terminal between the conductive pillar and the metal pad
Data Source
AI summary
A semiconductor package and a method of manufacturing the semiconductor package are provided. A method includes: forming a seed layer; forming a first photoresist pattern on the seed layer; forming a metal pad on the seed layer by using the first photoresist pattern; forming a second photoresist pattern on the seed layer; forming a conductive post on the seed layer by using the second photoresist pattern; providing, on the metal pad, a first semiconductor chip on which a conductive pillar and an insulating material layer surrounding a sidewall of the conductive pillar are formed; bonding the first semiconductor chip to the metal pad by using a connection terminal; forming a first molding layer surrounding the first semiconductor chip; removing the connection terminal and the metal pad; and forming a redistribution structure connected to the conductive pillar.