Semiconductor Package Assembly for Low-Stress Die Bonding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The coefficient of thermal expansion mismatch between different materials in semiconductor packaging causes stress and delamination, leading to potential damage during manufacturing and use.
Innovation Solution
The use of a carrier substrate with tested and good interconnect structures, encapsulated in a first encapsulant, and bonded with semiconductor dies using low-temperature Cu-to-Cu bonding or solder bonding, followed by encapsulation in a second encapsulant, to minimize thermal stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional solder bump packaging is used to connect semiconductor die to external devices, then electrical connection is achieved, but coefficient of thermal expansion mismatch causes stress and delamination at elevated temperatures
Solution Approach 1:
The patent changes the bonding temperature parameter from traditional high-temperature solder reflow to low-temperature Cu-to-Cu bonding (below 250°C), which reduces thermal stress and prevents delamination while maintaining connection reliability
Solution Approach 2:
The patent uses a composite interconnect structure with multiple layers including Cu-polyimide-Cu configurations, where the polyimide layer acts as a stress buffer to accommodate coefficient of thermal expansion mismatch between different materials, preventing delamination
2Adaptability or versatility
If multiple layers of different materials are stacked to form semiconductor die, then functional complexity is achieved, but each material's unique coefficient of thermal expansion causes stress at elevated temperatures
Solution Approach 1:
The patent modifies the bonding temperature parameter to low-temperature processing, which reduces thermal expansion differences between materials and minimizes stress accumulation in multi-layer structures
Solution Approach 2:
The patent introduces polyimide layers as intermediary materials between copper interconnect layers, where the polyimide serves as a compliant buffer that accommodates differential thermal expansion and prevents stress-induced delamination
3Object-affected harmful factors
If low-temperature Cu-to-Cu bonding is used instead of traditional solder bonding, then thermal stress is reduced, but manufacturing process complexity changes
Solution Approach 1:
The patent changes the bonding temperature parameter to low-temperature range and modifies the bonding mechanism from solder-based to direct Cu-to-Cu bonding, which reduces thermal stress while requiring precise control of bonding parameters to ensure manufacturing quality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces delamination and enhances board level reliability, allowing for super large package components suitable for high-performance computing applications with improved electrical performance and reliability.
Implementation Method 1
Each one of these different materials may have a unique coefficient of thermal expansion that is different from the other materials. This type of coefficient of thermal expansion mismatch causes each one of the materials to expand a different distance when the semiconductor die is heated during later processing, testing or use.
Implementation Method 2
bonded with semiconductor dies using low-temperature Cu-to-Cu bonding or solder bonding
Data Source
AI summary
A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.