Semiconductor Package RDL and Through-Via Layout for Die Communication
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Solution Overview
Problem
As semiconductor package sizes increase for high-performance computing applications, communication between dies becomes more challenging, requiring effective solutions for efficient electrical connections and data transfer.
Innovation Solution
The method involves fabricating a semiconductor package with a circuit board structure, redistribution layers, and encapsulants to facilitate electrical connections between dies and package components, enhancing communication and data transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the package size is increased for high-performance computing applications, then the bandwidth and data rate are improved, but the communication between dies becomes more challenging and latency increases
Solution Approach 1:
The patent transitions from traditional two-dimensional planar packaging to three-dimensional vertical stacking architecture. Multiple dies are stacked vertically and interconnected through through-silicon vias (TSVs), enabling high-bandwidth communication while maintaining short signal paths. This dimensional change allows simultaneous achievement of high bandwidth through parallel vertical channels and low latency through minimized inter-die distance.
Solution Approach 2:
The patent implements nested packaging where multiple dies are stacked vertically within a compact package structure. Each die is nested above or below others, with interconnect structures (TSVs, redistribution layers) nested within the die stack. This nested arrangement maximizes communication bandwidth through parallel vertical interconnects while keeping the overall package footprint small and signal paths short.
2Productivity
If the package size is increased, then more dies can be included for higher performance, but communication between dies becomes more challenging
Solution Approach 1:
The patent uses vertical stacking to increase the number of dies within a compact package. Instead of expanding horizontally which increases communication distance and complexity, dies are arranged vertically with standardized interconnect structures (TSVs, redistribution layers) that simplify the communication architecture despite increased die count.
Solution Approach 2:
The patent employs universal interconnect structures such as through-silicon vias (TSVs) and redistribution layers that serve multiple functions: electrical connection, signal routing, and mechanical support. These multi-functional structures simplify the overall communication architecture by providing standardized interfaces between dies, reducing the complexity of inter-die communication even as the number of dies increases.
3Power
If traditional packaging is used, then manufacturing is simpler, but electrical connections and data transfer efficiency are insufficient for high-performance computing
Solution Approach 1:
The patent performs preliminary actions during die fabrication by pre-forming through-silicon vias (TSVs), embedding conductive structures, and creating redistribution layers before the actual packaging assembly. This preliminary preparation of interconnect structures enables efficient post-bonding electrical connections and high-speed data transfer, while the standardized pre-formed structures actually simplify the overall manufacturing process by reducing on-site assembly complexity.
Data Source
AI summary
A method of manufacturing a semiconductor package includes the following steps. A first redistribution layer structure is formed over a circuit board structure. A through via is formed over the first redistribution layer structure. A first die is mounted onto the first redistribution layer structure aside the through via. A first encapsulant is formed to encapsulate the first die and the through via, wherein surfaces of the first encapsulant, the first die and the through via are substantially coplanar.