Semiconductor Package Structure for High-Density Die Stacking
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturization and packaging techniques for System-on-Integrated-Circuit (SoIC) components, particularly in achieving smaller, faster, and more efficient integration of semiconductor dies with lower power consumption and latency, due to limitations in current packaging methods.
Innovation Solution
The method involves a process flow for fabricating an integrated fanout package structure using chip-to-wafer fusion bonding and hybrid bonding techniques, where bottom tier semiconductor dies are bonded to a carrier using silicon dioxide or silicon oxynitride bonding layers, followed by insulating encapsulation, thinning, and bonding enhancement films to enable efficient integration of top tier semiconductor dies, allowing for flexible placement and electrical connectivity without size constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional packaging methods are used for semiconductor dies, then manufacturing process is simpler, but integration density is lower and device size is larger
Solution Approach 1:
The packaging process is divided into multiple tiers (bottom tier and top tier) with distinct functions. The bottom tier handles routing and interconnection, while the top tier contains the active die, allowing complex functionality to be achieved through modular assembly rather than a single complex packaging step
Solution Approach 2:
The patent transitions from traditional 2D packaging to 3D stacked architecture by vertically stacking multiple semiconductor dies with routing layers in between. This vertical integration enables higher integration density without increasing the horizontal footprint of the device
2Volume of moving object
If System-on-Integrated-Circuit components are used for compactness, then device size is reduced, but power consumption and latency challenges arise
Solution Approach 1:
The patent creates localized functional regions with the die stacked directly over the routing tier, minimizing signal path lengths. This local integration reduces the distance electrons must travel, thereby reducing power consumption and latency while maintaining compact form factor
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances integration density, reduces power consumption, and improves bandwidth by enabling compact and efficient packaging of semiconductor dies, allowing for increased functionality and reduced latency in SoIC components.
Implementation Method 1
bottom tier semiconductor dies are bonded to a carrier using silicon dioxide or silicon oxynitride bonding layers
Data Source
AI summary
A package structure including a first semiconductor die, a first insulating encapsulation, a bonding enhancement film, a second semiconductor die and a second insulating encapsulation is provided. The first insulating encapsulation laterally encapsulates a first portion of the first semiconductor die. The bonding enhancement film is disposed on a top surface of the first insulating encapsulation and laterally encapsulates a second portion of the first semiconductor die, wherein a top surface of the bonding enhancement film is substantially leveled with a top surface of the semiconductor die. The second semiconductor die is disposed on and bonded to the first semiconductor die and the bonding enhancement film. The second insulating encapsulation laterally encapsulates the second semiconductor die.