Semiconductor Package Recessed Dielectric Buffer Against Chip Tearing

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Solution Overview

Problem

The thermal expansion of the molding compound in semiconductor packages often causes tearing forces that separate the chips, leading to structural integrity issues.

Innovation Solution

Incorporating a dielectric layer between the chips, which is formed within a recess on one chip and bonded to the bonding layers of both chips, reducing the tearing force by acting as a buffer against thermal expansion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If molding compound is used to cover the chip, then the chip is protected and packaged, but thermal expansion of the molding compound generates tearing forces that separate the chips

Engineering Contradiction:

Improvechip bonding reliabilityVSAvoidtearing force

Core Design Contradiction:

ReliabilityVSForce

Solution Approach 1:

A dielectric layer is introduced as an intermediary between the first chip and the molding compound. This dielectric layer acts as a buffer that absorbs and mitigates the tearing forces generated by thermal expansion of the molding compound, preventing direct transmission of these forces to the chip bonding interface.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The dielectric layer is placed beforehand between the chip and molding compound to provide cushioning against the anticipated thermal expansion forces. This pre-positioned buffer layer absorbs the mechanical stress before it can reach the chip bonding interface, protecting the structure in advance of thermal cycling events.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

2Force

If a dielectric layer is added between chips, then tearing force is reduced, but device complexity increases

Engineering Contradiction:

Improvetearing force reductionVSAvoidpackage structure complexity

Core Design Contradiction:

ForceVSDevice complexity

Solution Approach 1:

The dielectric layer serves multiple functions simultaneously: it acts as an electrical insulator between chips, provides mechanical cushioning against thermal expansion forces, and serves as an adhesive bonding layer. By combining these functions into a single layer, the solution reduces overall device complexity compared to using separate layers for each function.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The dielectric layer effectively mitigates the tearing forces, ensuring the chips remain bonded even under thermal stress, enhancing the structural integrity of the semiconductor package.

Implementation Method 1

the dielectric layer may reduce the tearing force resulted from the thermal expansion of the molding compound

Methodology Applied

Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS20250323177A1Semiconductor package and manufacturing method thereof

Publication Date: 2025.10.16 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor package includes a first chip, a second chip, a molding compound and a dielectric layer. The second chip has a lateral surface, a lower surface and a recess recessed with respect to the lower surface. The molding compound is formed on the lateral surface of the second chip. The dielectric layer is formed within the recess.