Semiconductor Package Dielectric Layer Surface Uniformity Control
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Solution Overview
Problem
Current semiconductor device packages face challenges in increasing input/output (I/O) counts due to low yield of conductive patterns with ultra-fine line widths and spacings, which limits their density and thickness.
Innovation Solution
A semiconductor device package is designed with a dielectric layer having a surface uniformity of less than 5% and a conductive pattern with line widths ranging from 0.5 μm to 2 μm, formed using a spin coating process with controlled gas flow, enabling high-density I/O counts without increasing package area and reducing warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the line width and spacing of the conductive pattern are shrunk to increase I/O density, then the I/O counts can be increased, but the yield of conductive pattern formation becomes low
Solution Approach 1:
The patent applies parameter changes by controlling the gas flow rate during spin coating to optimize the dielectric layer formation. By adjusting the gas flow rate parameter, the patent achieves uniform dielectric layers that enable high-yield formation of conductive patterns with ultra-fine line widths and spacing, thus resolving the contradiction between increasing I/O density and maintaining manufacturing yield
Solution Approach 2:
The patent utilizes pneumatics by introducing a gas flow during the spin coating process to control the dielectric material deposition. The gas flow affects the distribution and uniformity of the dielectric layer, which in turn enables precise formation of conductive patterns at ultra-fine dimensions while maintaining high yield
2Length of moving object
If the dielectric layer thickness is reduced to achieve thinner package, then the package thickness can be decreased, but the surface uniformity becomes difficult to control
Solution Approach 1:
The patent employs pneumatic control through gas flow during spin coating to achieve uniform dielectric layers at reduced thickness. The gas flow parameters are optimized to ensure that even at thin dielectric layer configurations, the surface uniformity remains within acceptable limits, enabling thinner packages without sacrificing manufacturing precision
Solution Approach 2:
The patent changes process parameters, specifically the gas flow rate during spin coating, to control the dielectric layer formation. By optimizing these parameters, the patent achieves both reduced dielectric layer thickness and maintained surface uniformity, resolving the contradiction between package thinning and surface quality control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the yield of conductive pattern formation, achieves high-density I/O counts, and alleviates warpage, thereby improving the reliability and performance of semiconductor device packages.
Implementation Method 1
a gas flow is provided by the gas flow control unit to blow the dielectric material to form a dielectric layer having a surface with a surface uniformity substantially equal to or less than 5%
Implementation Method 2
A dielectric material is formed on the first carrier, and a gas flow is provided by the gas flow control unit to blow the dielectric material to form a dielectric layer
Data Source
AI summary
A semiconductor device package includes a dielectric layer, a first conductive pattern and a first semiconductor device. The dielectric layer has a first surface, wherein a surface uniformity of the first surface is substantially equal to or less than 5%. The first conductive pattern is disposed on the first surface of the dielectric layer, wherein the first conductive pattern includes a first conductive trace, and a line width of the first conductive trace substantially ranges from about 0.5 μm and about 2 μm. The first semiconductor device is disposed on the first surface of the dielectric layer and electrically connected to the first conductive pattern.