Semiconductor Package Dielectric Layers for Fine-Pitch Trace Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor device package manufacturing, misalignment and warpage issues lead to inaccuracies in forming conductive traces, resulting in electrical problems such as shorts or opens, especially when fine-pitch traces are involved.
Innovation Solution
The semiconductor device package design includes a first and second dielectric layer with conductive layers, where the dielectric layers are formed with specific thickness and material properties to ensure accurate alignment and electrical connection, and a method involving photosensitive materials and lithographic techniques to form precise conductive traces with controlled misalignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If fine-pitch conductive traces are formed on one side of the circuit layer and coarse-pitch conductive traces are formed on the other side, then the connection structure can be established, but misalignment and leveling errors cause inaccurate trace formation resulting in electrical problems
Solution Approach 1:
The patent introduces a intermediate carrier layer between the first and second circuit layers, creating a three-dimensional stacked structure. This dimensional approach allows the fine-pitch traces on the first circuit layer to be aligned with coarse-pitch traces on the second circuit layer through the carrier, resolving the misalignment issue by separating the trace formation planes in the z-direction rather than attempting to align them on the same plane.
Solution Approach 2:
The carrier acts as an intermediary element that receives the first circuit layer with fine-pitch traces and provides a stable platform for forming the second circuit layer with coarse-pitch traces. This intermediary structure compensates for misalignment and leveling errors by providing reference surfaces and alignment features that enable accurate trace formation despite manufacturing tolerances.
2Manufacturing precision
If coarse-pitch conductive traces are formed first and then fine-pitch conductive traces are formed on the chip-side, then the connection structure can be built, but warpage issues make it difficult to form accurate traces
Solution Approach 1:
The patent performs preliminary actions by first forming the coarse-pitch traces on the carrier, then bonding the first circuit layer with fine-pitch traces to the carrier before forming the second circuit layer. This sequence stabilizes the structure early in the process, preventing warpage from developing during subsequent processing steps and ensuring accurate trace formation throughout manufacturing.
Solution Approach 2:
By stacking the circuit layers in three dimensions with the carrier in between, the patent eliminates the warpage issue that occurs when attempting to form both trace types on a single planar layer. The vertical separation allows each layer to be formed independently on a stable surface, preventing the dimensional instability and warping that would occur in a two-dimensional approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach facilitates the accurate formation of fine-pitch conductive traces with reduced misalignment, enhancing the reliability of semiconductor device packages by preventing electrical issues like shorts or opens.
Implementation Method 1
exposing and developing the photosensitive material and removing a portion of the photosensitive material to form a first circuit layer
Data Source
AI summary
A semiconductor device package includes a first dielectric layer, a first conductive layer, an electronic component, a second dielectric layer, a second conductive layer and a package body. The first dielectric layer has a top surface, a bottom surface opposite to the top surface and a lateral surface extending between the top surface and the bottom surface. The first conductive layer is disposed on the top surface of the first dielectric layer. The electronic component is disposed on the top surface of the first dielectric layer. The second dielectric layer covers the bottom surface and a first portion of the lateral surface of the first dielectric layer and exposes a second portion of the lateral surface of the first dielectric layer. The second conductive layer is disposed on a bottom surface of the second dielectric layer and electrically connected to the first conductive layer. The package body covers the electronic component, the top surface of the second dielectric layer and the second portion of the lateral surface of the first dielectric layer.