Semiconductor Package With Direct-Bonded-Metal Substrate for Thermal Management

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Solution Overview

Problem

Thermal interface materials (TIMs) increase thermal resistance between semiconductor devices and external heat transfer mechanisms, leading to excessive heating and reduced reliability, while also increasing manufacturing costs.

Innovation Solution

A semiconductor device package design featuring a die attach paddle and a direct-bonded-metal substrate with a ceramic layer that electrically isolates the external thermal dissipation surface, eliminating the need for TIMs and reducing thermal resistance by allowing direct heat transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a thermal interface material (TIM) is used to provide electrical isolation between the external heat transfer mechanism and the thermal dissipation surface, then electrical isolation is achieved, but thermal resistance increases

Engineering Contradiction:
Improveelectrical isolationVSAvoidthermal resistance
Core Design Contradiction:
ReliabilityVSTemperature

Solution Approach 1:

The patent introduces a ceramic layer as an intermediary substance between the first metal layer (connected to semiconductor device) and the second metal layer (external thermal dissipation surface). This ceramic intermediary provides electrical isolation while maintaining thermal conduction, thereby resolving the contradiction between achieving electrical isolation and minimizing thermal resistance.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If a thermal interface material (TIM) is used to provide electrical isolation, then electrical isolation is achieved, but manufacturing costs increase

Engineering Contradiction:
Improveelectrical isolationVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The ceramic layer serves as a cost-effective intermediary that integrates electrical isolation functionality directly into the package structure. This eliminates the need for separate TIM materials and associated manufacturing operations, thereby reducing manufacturing costs while maintaining electrical isolation.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Temperature

If direct heat transfer is enabled by eliminating TIM, then thermal resistance decreases, but electrical isolation may be compromised

Engineering Contradiction:
Improvethermal resistanceVSAvoidelectrical isolation
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The patent employs a composite structure consisting of a ceramic layer bonded to metal layers (forming a DBM substrate). This composite material combination leverages the electrical insulation properties of ceramics while maintaining thermal conduction capabilities, enabling direct heat transfer without compromising electrical isolation.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design significantly reduces thermal resistance, enhances semiconductor device reliability, and lowers manufacturing costs by eliminating the need for TIMs and associated manufacturing operations.

Implementation Method 1

The second metal layer can be electrically isolated from the first metal layer by the ceramic layer

Methodology Applied
Scientific EffectElectrical insulation: Dielectric

Implementation Method 2

reducing thermal resistance by allowing direct heat transfer

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS11521921B2Semiconductor device package assemblies and methods of manufacture
Publication Date: 2022.12.06 SEMICON COMPONENTS IND LLC
  • US11521921B2 patent drawing
  • US11521921B2 patent drawing
  • US11521921B2 patent drawing

AI summary

In one general aspect, a semiconductor device package can include a die attach paddle having a first surface and a second surface that is opposite the first surface. The package can also include a semiconductor die coupled with the first surface of the die attach paddle. The package can further include a direct-bonded-metal (DBM) substrate. The DBM substrate can include a ceramic layer having a first surface and a second surface that is opposite the first surface; a first metal layer disposed on the first surface of the ceramic layer and coupled with the second surface of the die attach paddle; and a second metal layer disposed on the second surface of the ceramic layer. The second metal layer can be exposed external to the semiconductor device package. The second metal layer can be electrically isolated from the first metal layer by the ceramic layer.