Semiconductor Package Cooling Structure for Dual-Side Heat Dissipation
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Solution Overview
Problem
Current semiconductor devices, particularly in high current applications like three-phase motor drivers, face challenges in efficiently dissipating heat due to reliance on single-side cooling methods, leading to thermal bottlenecks and reduced power density.
Innovation Solution
The implementation of a semiconductor device design that includes multiple chip packages with encapsulation, contact structures, and a cooling element thermally connected to protruding cooling structures, allowing for both top and bottom side cooling, thereby enhancing heat dissipation and reducing thermal resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If single-side cooling is used, then device structure is simple, but thermal performance is insufficient
Solution Approach 1:
The patent transitions from single-side cooling to dual-side cooling by adding cooling capability in another dimension (the opposite side of the chip). The first cooling structure is arranged on the first side of the chip, and the second cooling structure is arranged on the second side of the chip, enabling heat dissipation from both sides simultaneously and improving thermal performance without excessive complexity.
2Loss of energy
If multiple cooling structures are added, then heat dissipation improves, but device space increases
Solution Approach 1:
The cooling system is segmented into multiple independent cooling structures: a first cooling structure on the first side of the chip, a second cooling structure on the second side of the chip, and a third cooling structure on the carrier. This segmentation allows each cooling structure to be optimized independently and distributed across different spatial locations, improving heat dissipation efficiency without requiring a single large cooling area.
Solution Approach 2:
The patent utilizes the third dimension (vertical stacking) by arranging cooling structures on both sides of the chip and on the carrier beneath. This multi-layer cooling arrangement enables efficient heat dissipation while maintaining a compact footprint on the carrier surface, as heat is removed through multiple pathways in different spatial dimensions.
3Temperature
If cooling structures protrude from encapsulation, then cooling efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The cooling structures are designed to protrude from the encapsulation material before final packaging, allowing thermal contact with the chip to be established early in the manufacturing process. This preliminary arrangement of cooling structures enables more flexible integration and reduces the complexity of subsequent assembly steps, as the cooling paths are pre-established rather than requiring complex post-assembly modifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves thermal performance by up to 20% junction-to-carrier thermal resistance and increases power dissipation, reducing parasitic inductance and resistance, and enhancing power density without requiring additional carrier space.
Implementation Method 1
a cooling element thermally conductively connected to at least one cooling structure of each of at least two of the plurality of semiconductor chip packages
Data Source
AI summary
A semiconductor device includes: a carrier including an electronic circuit; a plurality of semiconductor chip packages mounted on the carrier, each of the chip packages including an encapsulation encapsulating the semiconductor chip, a plurality of contact structures electrically connecting the semiconductor chip with the electronic circuit, and at least one cooling structure protruding from the encapsulation; and a cooling element thermally conductively connected to at least one cooling structure of each of at least two of the plurality of semiconductor chip packages.