Semiconductor Package Warpage Control via Dual CTE Molding Layers
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Solution Overview
Problem
Three-dimensional semiconductor device packages experience warpage due to asymmetrical structures and material mismatches, particularly a mismatch in coefficients of thermal expansion (CTE), which is not effectively addressed by increasing package thickness, conflicting with the trend of miniaturizing electronic products.
Innovation Solution
A semiconductor device package design featuring two molding layers with different coefficients of thermal expansion (CTE) is implemented, where the first molding layer encapsulates electrical elements on one surface and the second molding layer encapsulates electronic components on the opposite surface, using various materials and filler sizes to match and adjust CTE, thereby alleviating warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the thickness of the semiconductor package is increased to alleviate warpage, then warpage is reduced, but the package size increases which conflicts with miniaturization trends
Solution Approach 1:
The molding layer is divided into multiple segments (first molding layer and second molding layer) with different CTE values. The first molding layer has a CTE matched to the circuit layer, while the second molding layer has a CTE matched to the electronic component, creating a gradient structure that progressively compensates for thermal expansion mismatch and reduces warpage without increasing overall thickness.
Solution Approach 2:
Different regions of the package structure are assigned different material properties. The first molding layer uses a material with CTE matched to the circuit layer for the electrical element encapsulation region, while the second molding layer uses a material with CTE matched to the electronic component for the component encapsulation region, optimizing local thermal compatibility.
2Stability of the object's composition
If molding materials with matched CTE are selected, then warpage is reduced, but material selection and process complexity increase
Solution Approach 1:
The molding function is segmented into two distinct layers with different material compositions and CTE values. This segmentation allows each layer to be optimized for its specific encapsulation region's thermal requirements, reducing overall warpage while maintaining manageable process complexity through systematic material selection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces warpage while maintaining a compact package size, enhancing the compatibility and performance of semiconductor devices by controlling thermal expansion mismatch and allowing for reduced height and improved signal routing.
Implementation Method 1
a mismatch of coefficients of thermal expansion (CTE)... the first molding layer and the second molding layer include different molding materials
Data Source
AI summary
A semiconductor device package includes: (1) a first circuit layer including a first surface and a second surface opposite to the first surface; (2) at least one electrical element disposed over the first surface of the first circuit layer and electrically connected to the first circuit layer; (3) a first molding layer disposed over the first surface of the first circuit layer, wherein the first molding layer encapsulates an edge of the at least one electrical element; (4) first electronic components disposed over the second surface of the first circuit layer and electrically connected to the first circuit layer; and (5) a second molding layer disposed over the second surface of the first circuit layer and encapsulating the first electronic components, wherein the first molding layer and the second molding layer include different molding materials.