Semiconductor Package Layout With Dual Redistribution Layers
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving a balance between size reduction, increased integration density, and improved electrical and reliability characteristics.
Innovation Solution
The semiconductor package incorporates a first redistribution layer with passive devices and a bridge structure, a second redistribution layer electrically connected to these components, and conductive structures between the layers, allowing for the mounting of semiconductor chips and chip stacks with enhanced electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional semiconductor package structures are used with bonding wires or bumps, then electrical connectivity is achieved, but the package size cannot be reduced and integration density is limited
Solution Approach 1:
The patent transitions from planar 2D wiring to 3D vertical stacking by introducing multiple redistribution layers (first and second redistribution layers) at different heights, connected through conductive structures. This dimensional change enables compact package size while maintaining electrical connectivity through vertical interconnections rather than lateral routing.
Solution Approach 2:
The patent implements nested structures where the first redistribution layer is positioned within the vertical space defined by the second redistribution layer. The conductive structures are nested within vias or openings in the substrate, and passive devices are integrated within the same vertical column as active devices, achieving high integration density in a compact volume.
2Quantity of substance
If more devices are integrated in the same area, then integration density increases, but electrical characteristics and reliability deteriorate
Solution Approach 1:
The patent resolves the trade-off between integration density and electrical characteristics by moving from 2D lateral arrangement to 3D vertical stacking. Multiple devices and interconnection layers are arranged in the vertical dimension, allowing high integration density while maintaining short electrical paths and good signal integrity through the conductive structures connecting the redistribution layers.
Solution Approach 2:
The patent segments the interconnection system into multiple functional layers: first redistribution layer for initial signal routing, second redistribution layer for final routing, and conductive structures for vertical interconnection. This segmentation allows each layer to be optimized independently for its specific function, maintaining electrical characteristics while achieving high integration density.
3Volume of moving object
If package size is reduced, then integration density increases, but fabrication complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the first redistribution layer and its conductive structures before mounting the semiconductor chip. The first redistribution layer is prepared in advance on the substrate, and its conductive structures are pre-formed to establish the interconnection framework before the chip is attached and wired, simplifying the overall fabrication sequence.
Data Source
AI summary
A semiconductor package may include a first redistribution layer, a passive device disposed on a top surface of the first redistribution layer, a bridge structure disposed on the top surface of the first redistribution layer and laterally spaced apart from the passive device, a second redistribution layer disposed on and electrically connected to the passive device and the bridge structure, conductive structures disposed between the first redistribution layer and the second redistribution layer and laterally spaced apart from the passive device and the bridge structure, a first semiconductor chip mounted on a top surface of the second redistribution layer, and a second semiconductor chip mounted on the top surface of the second redistribution layer. The conductive structures may include a signal structure and a ground/power structure, which is laterally spaced apart from the signal structure and has a width larger than the signal structure.