Semiconductor Package with Dual-Surface I/O for Face-to-Face Bonding
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Solution Overview
Problem
The integration of electronic components such as memory devices and ASICs often requires additional redistribution structures and conductive pillars due to size differences, increasing manufacturing costs and thickness, while face-to-face bonding is needed to enhance performance, but this restricts I/O terminal arrangement and bandwidth.
Innovation Solution
A semiconductor package structure with I/O terminals on two opposite surfaces, featuring a high density conductive layer for high-speed signal transmission and a low density conductive layer for power transmission, allowing for face-to-face electronic component connection without additional redistribution structures, thereby enhancing signal transmission capacity and reducing propagation delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If face-to-face bonding of ASIC with memory device is adopted to provide shorter transmission path, then signal transmission speed is improved, but additional redistribution structures and conductive pillars are needed due to size difference, increasing manufacturing cost and thickness
Solution Approach 1:
The patent transitions from traditional single-surface I/O arrangement to a dual-surface configuration, utilizing both the first and second opposite surfaces of the substrate for I/O terminals. This dimensional change allows direct face-to-face bonding without requiring additional redistribution structures or conductive pillars, thereby maintaining high signal transmission speed while eliminating manufacturing complexity associated with size matching between different components
2Ease of manufacture
If additional redistribution structures and conductive pillars are added to accommodate size difference, then connection between ASIC and memory device is achieved, but overall package thickness is increased
Solution Approach 1:
By distributing I/O terminals across two opposite surfaces of the substrate, the patent eliminates the need for thick redistribution structures and conductive pillars that would be required for single-surface connections. This dual-surface approach achieves component connection while minimizing the overall package thickness, as the connection path becomes more direct and requires fewer intermediate layers
3Ease of manufacture
If I/O terminals are arranged on a single surface, then manufacturing process is simplified, but signal transmission capacity and bandwidth are limited
Solution Approach 1:
The patent utilizes both opposite surfaces of the substrate for I/O terminal arrangement, effectively doubling the available surface area for signal connections. This dual-surface configuration increases signal transmission capacity and bandwidth without complicating the manufacturing process, as each surface can be independently processed and connected to corresponding terminals on the bonded component
4Productivity
If substrate surface area is fully utilized for high-speed signal transmission, then bandwidth is enhanced, but power transmission capability may be compromised
Solution Approach 1:
The patent segments the substrate into distinct functional regions: a first region on the first surface for high-speed signal transmission and a second region on the second surface for power transmission. This segmentation allows each surface to be optimized for its specific function, with the signal transmission region providing high bandwidth and the power transmission region ensuring adequate power delivery, without one function compromising the other
Data Source
AI summary
A package structure is provided. The package structure includes a semiconductor substrate. The semiconductor substrate includes a lower portion and an upper portion. The upper portion of the semiconductor substrate defines a high speed signal transmission region. The high speed signal transmission region includes a first region configured to communicate with a first electronic component and a second region configured to communicate with an external device. The lower portion of the semiconductor substrate defines a power transmission region