Semiconductor Package Stacking With Dummy Bumps to Prevent Shorts
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Solution Overview
Problem
In semiconductor chip stacking processes, the deformation of solder bumps during temperature-compression bonding can lead to defects such as short circuits, reducing the reliability of the semiconductor package.
Innovation Solution
The use of dummy bumps between the memory chip bumps minimizes the flowability of the non-conductive film during the bonding process, preventing short circuits and improving contact reliability by controlling the flow of the adhesive layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If temperature-compression bonding is used to stack chips, then chip stacking is achieved, but solder bumps deform leading to short circuits
Solution Approach 1:
A non-conductive film is introduced as an intermediary layer between the lower chip and upper chip during temperature-compression bonding. This film mediates the bonding process by providing a controlled interface that prevents direct metal-to-metal contact and solder bump deformation, thereby avoiding short circuits while enabling reliable chip stacking.
Solution Approach 2:
The bonding process parameters are optimized by controlling temperature, pressure, and bonding time during temperature-compression bonding. By carefully adjusting these parameters, the process achieves reliable chip stacking while minimizing solder bump deformation and preventing short circuits between adjacent bumps.
2Reliability
If solder bumps are used to connect stacked chips, then electrical connection is achieved, but bumps deform during manufacturing
Solution Approach 1:
The non-conductive film serves as a mediator during the bonding process, protecting the solder bumps from deformation while maintaining electrical connection integrity. This intermediary layer simplifies manufacturing by preventing defects without compromising connection reliability.
Solution Approach 2:
The non-conductive film provides beforehand cushioning to the solder bumps during the bonding process. This protective layer absorbs and distributes pressure uniformly, preventing bump deformation before it can occur, thereby reducing manufacturing defects while maintaining connection reliability.
3Reliability
If adhesive layer is used for chip bonding, then chip stacking is achieved, but adhesive flow causes poor contact
Solution Approach 1:
The non-conductive film acts as an intermediary that controls adhesive layer flow during bonding. This film provides a defined interface that guides adhesive distribution, ensuring uniform contact between chips while preventing adhesive from flowing into areas that would cause poor contact or short circuits.
Solution Approach 2:
The viscosity and flow characteristics of the adhesive layer are controlled by adjusting bonding temperature and pressure parameters. By optimizing these parameters, the adhesive achieves proper flow to ensure good contact between chips without excessive flow that would cause poor contact in critical areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of the semiconductor package by reducing the occurrence of short circuits and poor contacts between bumps, thereby increasing the overall reliability and simplifying the chip fabrication process.
Implementation Method 1
semiconductor chips are stacked by using a thermo-compression bonding (TCB) method
Data Source
AI summary
The present disclosure relates to a semiconductor package and a manufacturing method thereof. The method includes stacking semiconductor chips using a thermo-compression bonding (TCB) method, where defects are minimized for increased reliability. The semiconductor package includes an interface chip including a first test pad, a bump pad provided inside the first test pad, and a first through silicon via (TSV) provided between the first test pad and the bump pad; at least one memory chip, which is stacked on the interface chip and includes a second test pad, a dummy pad provided inside the second test pad, and a second TSV provided between the second test pad and the dummy pad; and an adhesive layer provided between the interface chip and the at least one memory chip. wherein no bump is provided on the first test pad and the second test pad.