Semiconductor Package Stacking With Dummy Bumps to Prevent Shorts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor chip stacking processes, the deformation of solder bumps during temperature-compression bonding can lead to defects such as short circuits between adjacent bumps, reducing the reliability of the semiconductor package.
Innovation Solution
The introduction of dummy bumps between the memory chip bumps minimizes the flowability of the non-conductive film during the bonding process, preventing short circuits and improving contact reliability by controlling the flow of the adhesive layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If temperature-compression bonding is used to stack chips, then chip stacking is achieved, but solder bumps deform leading to short circuits between adjacent bumps
Solution Approach 1:
A non-conductive film is introduced as an intermediary substance between adjacent solder bumps during the bonding process. This film prevents direct contact between bumps, eliminating the short circuit issue while allowing the temperature-compression bonding process to proceed effectively for chip stacking.
Solution Approach 2:
The harmful flowability of the non-conductive film is selectively removed or minimized in specific areas where it would cause bumps to deform and short circuit. This is achieved by controlling the film's properties or removing excess film in critical regions, while maintaining its presence in areas where it provides beneficial separation.
2Ease of manufacture
If solder bumps are used to connect stacked chips, then electrical connection is achieved, but bumps deform during manufacturing causing defects
Solution Approach 1:
The non-conductive film serves as a mediator that stabilizes the position of solder bumps during the manufacturing process. By providing a controlled interface between bumps, the film prevents deformation and maintains precise positioning, thereby improving manufacturing precision without complicating the connection process.
3Ease of manufacture
If non-conductive film is applied between chips, then bonding is facilitated, but film flow causes bump deformation and short circuits
Solution Approach 1:
The non-conductive film is applied with spatially varying properties - it is present in regions where bonding facilitation is needed, but its flowability is minimized or it is completely absent in regions where bump deformation would occur. This localized control of film properties allows the bonding process to proceed easily while preventing harmful bump deformation.
Solution Approach 2:
The flowability parameter of the non-conductive film is changed or controlled to prevent bump deformation. This may involve adjusting the film's viscosity, thickness, or chemical composition in specific areas, or controlling the bonding process parameters (temperature, pressure, time) to minimize film flow while maintaining effective bonding.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of the semiconductor package by reducing the occurrence of short circuits and poor contacts between bumps, thereby improving the overall performance and durability of the chip stacking process.
Implementation Method 1
semiconductor chips are stacked by using a thermo-compression bonding (TCB) method
Data Source
AI summary
The present disclosure relates to a semiconductor package and a manufacturing method thereof. The method includes stacking semiconductor chips using a thermo-compression bonding (TCB) method, where defects are minimized for increased reliability. The semiconductor package includes an interface chip including a first test pad, a bump pad provided inside the first test pad, and a first through silicon via (TSV) provided between the first test pad and the bump pad; at least one memory chip, which is stacked on the interface chip and includes a second test pad, a dummy pad provided inside the second test pad, and a second TSV provided between the second test pad and the dummy pad; and an adhesive layer provided between the interface chip and the at least one memory chip. wherein no bump is provided on the first test pad and the second test pad.