Semiconductor Package Dummy Conductive Connectors for Connection Testing
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Solution Overview
Problem
Semiconductor packages with stacked chips face challenges in reliability due to difficulties in detecting connection failures between chips, which affects the overall performance and durability of the package.
Innovation Solution
Incorporating dummy conductive connectors, including dummy wiring lines and through substrate vias, that are electrically connected to main through substrate vias on one end but not the other, allowing for electrical die sorting tests to be performed through test pads in the scribe regions, and sealing side surfaces with a molding member to enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If chips are stacked to achieve miniaturization and increased processing speed, then device density and performance improve, but reliability deteriorates due to difficulty in detecting connection failures between chips
Solution Approach 1:
The patent applies preliminary action by forming dummy through-substrate vias and dummy wiring lines in advance during chip fabrication, before the chips are stacked. These dummy structures are pre-positioned in scribe regions to enable subsequent electrical testing of inter-chip connections, allowing connection failures to be detected early in the manufacturing process rather than after assembly.
Solution Approach 2:
The patent uses dummy wiring lines as intermediary elements that connect main through-substrate vias to dummy through-substrate vias. These intermediary dummy wiring lines provide a test path that allows electrical signals to traverse through the stacked chip connections without carrying actual functional data, enabling independent verification of connection integrity separate from normal device operation.
2Volume of moving object
If conventional stacked chip structures are used, then device miniaturization is achieved, but measurement and detection of connection failures becomes difficult
Solution Approach 1:
The patent segments the detection function from the functional chip circuits by using separate dummy through-substrate vias and dummy wiring lines dedicated solely to testing. This segmentation allows the test path to be independently activated and measured without interfering with or being confused by the actual functional circuits, simplifying the detection of connection failures in the compact stacked structure.
Solution Approach 2:
The patent creates a copy of the through-substrate via structure by forming dummy through-substrate vias that replicate the geometry and positioning of the main through-substrate vias. These dummy vias serve as test duplicates that allow electrical measurement of the inter-chip connections without requiring access to the actual functional connection points, making detection easier in miniaturized packages.
3Reliability
If dummy conductive connectors are added to enable electrical die sorting tests, then reliability improves through better detection capability, but device complexity increases
Solution Approach 1:
The patent applies local quality by confining the dummy through-substrate vias and dummy wiring lines to specific scribe regions of the chip, rather than distributing them throughout the entire chip structure. This localized placement adds minimal complexity only where needed for testing, while leaving the functional chip areas unchanged and simple.
Solution Approach 2:
The dummy wiring lines and dummy through-substrate vias serve multiple functions: they provide a test path for electrical die sorting, they verify inter-chip connection integrity, and they do not interfere with functional circuits. This multi-functionality justifies the added structural elements by providing comprehensive testing capability without requiring separate dedicated test structures.
Data Source
AI summary
Semiconductor packages are disclosed. A semiconductor package includes: a first chip that includes a chip region and scribe regions at edges of the chip region, wherein the chip region comprises integrated circuit units and main through substrate vias electrically connected to the integrated circuit units; and a second chip that is bonded onto the first chip. The semiconductor package includes dummy conductive connectors including at least dummy wiring lines, the dummy conductive connectors electrically connected to the main through substrate vias at one end, and not capable of forming an electrical connection at the other end.