Semiconductor Package Structure with Dummy Dies for Planarization

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Solution Overview

Problem

The semiconductor industry faces challenges in achieving efficient integration and packaging of three-dimensional integrated circuits (3DICs) due to issues with bonding and planarization processes, which can lead to damage and topography degradation of dies during the formation of semiconductor package structures.

Innovation Solution

A method involving bonding dies to a wafer using hybrid or fusion bonding techniques, followed by the formation of a dielectric material layer and subsequent planarization processes to protect and cover the dies, reducing damage and maintaining the integrity of the semiconductor package structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If hybrid or fusion bonding techniques are used to bond dies to a wafer, then integration density and stacking efficiency are improved, but the risk of die damage and topography degradation increases

Engineering Contradiction:
Improveintegration densityVSAvoiddie integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A dielectric material layer is formed over the dies and dummy dies before bonding to the wafer. This preliminary formation of the dielectric layer protects the dies during subsequent bonding and planarization processes, preventing damage while enabling high-density integration

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dielectric material layer acts as an intermediary between the dies and the external environment during processing. It serves as a protective barrier that mediates the mechanical stresses and physical contact during bonding and planarization, reducing direct damage to the fragile dies

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If planarization processes are performed to remove dielectric material and maintain flat surfaces, then manufacturing precision is improved, but die damage and topography degradation worsen

Engineering Contradiction:
Improvesurface flatnessVSAvoiddie damage
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

Dummy dies are formed at edge locations with different properties than active dies. The dielectric material layer is selectively removed from dummy dies while being retained on active dies during planarization. This local differentiation allows the planarization process to achieve surface flatness without damaging the active dies, as the dummy dies serve as sacrificial elements

Inventive Principle:
Principle #3Local quality

3Reliability

If dummy dies are formed at edge locations to protect active dies, then die protection is improved, but chip area penalty increases

Engineering Contradiction:
Improvedie protectionVSAvoidchip area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

Dummy dies are formed as sacrificial, disposable elements at the edges of the wafer. These dummy dies are intentionally designed to be removed after serving their protective function during bonding and planarization. By using disposable dummy dies, the patent protects valuable active dies without permanently sacrificing chip area, as the dummy dies can be eliminated in subsequent processing steps

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the integration density and reduces chip area penalties by protecting the dies and maintaining the structural integrity of the semiconductor package, allowing for efficient stacking and further integration of components without significant topography degradation.

Implementation Method 1

forming a dielectric material layer on the wafer to cover the dies and the dummy dies

Methodology Applied
Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS11699694B2Method of manufacturing semiconductor package structure
Publication Date: 2023.07.11 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11699694B2 patent drawing
  • US11699694B2 patent drawing
  • US11699694B2 patent drawing

AI summary

Methods of manufacturing a semiconductor package structure are provided. A method includes: bonding dies and dummy dies to a wafer; forming a dielectric material layer on the wafer to cover the dies and the dummy dies; performing a first planarization process to remove a first portion of the dielectric material layer over top surfaces of the dies and the dummy dies; and performing a second planarization process to remove portions of the dies, portions of the dummy dies and a second portion of the dielectric material layer, and a dielectric layer is formed laterally aside the dies and the dummy dies; wherein after the second planarization process is performed, a total thickness variation of the dies is less than a total thickness variation of the dummy dies.