Semiconductor Package Dummy Electrode Stress Distribution

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Solution Overview

Problem

Conventional semiconductor packages with high-density electrode arrays on the bottom surface of resin encapsulations face reliability issues due to crack generation at corners under external stress and temperature cycles, limiting the impact resistance and temperature cycle resistance of storage media.

Innovation Solution

Incorporating a semiconductor package design with signal electrodes in the central region of the array and dummy electrodes on the periphery, including additional dummy electrodes at the corners, to distribute stress and enhance adhesiveness, thereby improving impact resistance and temperature cycle resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If electrodes are arranged in a rectangular grid shape on the bottom surface of the resin encapsulation to achieve high density, then the storage medium can be downsized and semiconductor chip density increased, but cracks are easily generated at the corners under external stress and temperature cycles

Engineering Contradiction:
Improvesemiconductor chip densityVSAvoidimpact resistance and temperature cycle resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies local quality by differentiating the function and structure of electrodes at different locations. Corner electrodes are designed with larger area and different geometry compared to central electrodes, providing enhanced stress distribution capability at the vulnerable corner regions while maintaining standard electrode design in the central high-density array region.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The electrode array is segmented into distinct functional zones: corner electrodes with enhanced stress-resistant design and central electrodes optimized for signal transmission. This segmentation allows each zone to be optimized for its specific function, with corner electrodes handling mechanical stress and central electrodes handling high-density signal routing.

Inventive Principle:
Principle #1Segmentation

2Reliability

If corner electrodes are excluded from signal transmission to prevent crack generation, then reliability under stress is improved, but the number of usable electrodes decreases

Engineering Contradiction:
Improvecrack resistanceVSAvoidnumber of usable electrodes
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

Corner electrodes are given local quality enhancement through increased area and modified geometry, enabling them to simultaneously perform stress distribution and signal transmission functions, unlike conventional designs where corner electrodes are excluded from signaling.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The corner electrodes are designed to serve multiple functions: mechanical stress distribution and signal transmission. This multi-functionality allows the corner electrodes to contribute to both reliability improvement and maintaining electrode count for signal transmission.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If a large number of electrodes are placed on the bottom surface to achieve high density, then semiconductor chip density increases, but the complexity of the electrode array and potential for crack generation increases

Engineering Contradiction:
Improveelectrode densityVSAvoidelectrode array complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies local quality by making corner electrodes geometrically distinct from central electrodes. This local differentiation simplifies the overall design by providing a clear rule for corner electrode configuration, reducing design complexity while maintaining high density in the central region.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUSRE49332E1Storage medium and semiconductor package
Publication Date: 2022.12.13 KIOXIA CORP
  • USRE49332E1 patent drawing
  • USRE49332E1 patent drawing
  • USRE49332E1 patent drawing

AI summary

A semiconductor package includes a semiconductor chip formed with a non-volatile semiconductor memory, a resin encapsulation that encapsulates the semiconductor chip, electrodes in a lattice (solder balls) formed and arrayed in a lattice on a bottom surface of the resin encapsulation. The solder balls include a signal electrode formed within the central region of the array and a dummy electrode formed outside the signal electrode.