Semiconductor Package Marking Using Backside Dummy Patterns

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Solution Overview

Problem

Current marking techniques for semiconductor devices are inefficient as production rates increase, failing to meet the demand for quick and efficient marking of semiconductor packages with information such as company names, serial numbers, or lot numbers.

Innovation Solution

A semiconductor package manufacturing process involving a backside redistribution structure with a dummy pattern and a marking pattern on a first patterned dielectric layer, where the dummy pattern is overlapped with the semiconductor device, allowing for efficient marking without additional sacrificial layers, reducing production costs and package thickness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If current marking techniques are used for semiconductor devices, then marking information can be applied to the device, but the marking process becomes inefficient as production rates increase

Engineering Contradiction:
Improvemarking efficiencyVSAvoidmarking time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The marking pattern is formed during the die attach process by positioning the carrier with pre-formed marking features, rather than applying markings after device assembly. This preliminary action integrates marking into an existing manufacturing step, eliminating separate marking operations and improving productivity as production rates increase

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If additional sacrificial layers are added for marking, then marking capability is improved, but manufacturing complexity and cost increase

Engineering Contradiction:
Improvemarking capabilityVSAvoidstructure complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The carrier serves multiple functions: it provides mechanical support for die attachment, enables precise positioning, and incorporates marking features directly into its structure. By making the carrier multi-functional, the invention eliminates the need for separate sacrificial layers dedicated solely to marking, thereby reducing structural complexity while maintaining ease of manufacture

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The marking features are merged into the carrier structure itself, combining the support function and marking function into a single component. This integration eliminates the need for additional sacrificial layers, reducing both manufacturing steps and structural complexity

Inventive Principle:
Principle #5Merging (Combining)

3Ease of manufacture

If additional sacrificial layers are added for marking, then marking can be achieved, but package thickness increases

Engineering Contradiction:
Improvemarking capabilityVSAvoidpackage thickness
Core Design Contradiction:
Ease of manufactureVSLength of stationary object

Solution Approach 1:

The carrier is designed to perform multiple functions including mechanical support, positioning, and marking. By integrating marking capabilities into the existing carrier structure, the invention eliminates the need for additional sacrificial layers that would increase package thickness, thereby maintaining thin package profiles while achieving marking capability

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11923318B2Method of manufacturing semiconductor package
Publication Date: 2024.03.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11923318B2 patent drawing
  • US11923318B2 patent drawing
  • US11923318B2 patent drawing

AI summary

A method of manufacturing a semiconductor package includes the following steps. A backside redistribution structure is formed, wherein the backside redistribution structure comprises a first dielectric layer, and a redistribution metal layer over the first dielectric layer and comprising a dummy pattern. A semiconductor device is provided over the backside redistribution structure, wherein an active surface of the semiconductor device faces away from the backside redistribution structure, the semiconductor device is electrically insulated from the dummy pattern and overlapped with the dummy pattern from a top view of the semiconductor package. A front side redistribution structure is formed over the semiconductor device, wherein the front side redistribution structure is electrically connected to the semiconductor device. A patterning process is performed on the first dielectric layer to form a marking pattern opening exposing a part of the dummy pattern.