Semiconductor Package Dummy Pad Layout for Reliable Fine-Pitch Bonding
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Solution Overview
Problem
The reliability of semiconductor packages is reduced as connection pads become finer, leading to challenges in bonding and potential for squeeze out and erosion phenomena during chemical mechanical polishing (CMP) processes.
Innovation Solution
A semiconductor package design that includes a first structure with a first insulating layer, electrode pads, and dummy pads, where the dummy pads are arranged around the electrode pads with a gradually decreasing surface area ratio towards the side of the structure, and a second structure with similar features bonded to the first structure, enhancing bonding reliability and reducing step differences during CMP.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If connection pads are made finer to achieve miniaturization, then device size is reduced, but bonding reliability deteriorates due to squeeze out and erosion phenomena during CMP processes
Solution Approach 1:
The patent applies local quality by creating dummy pads with varying surface areas at different locations around the electrode pads. The dummy pads have larger surface areas near the electrode pads and gradually decrease in size toward the edge of the insulating layer, providing localized compensation for CMP erosion and squeeze out effects specifically where they occur most during the bonding process.
2Volume of moving object
If connection pads are made finer to achieve miniaturization, then device size is reduced, but manufacturing precision deteriorates due to bonding failures
Solution Approach 1:
The patent implements beforehand cushioning by pre-configuring dummy pads with gradually decreasing surface areas around the electrode pads before the CMP and bonding processes. These dummy pads serve as sacrificial structures that absorb CMP erosion and squeeze out effects in advance, protecting the actual electrode pads from damage and ensuring precise bonding alignment.
3Ease of manufacture
If dummy pads with uniform surface area are used, then manufacturing is simplified, but CMP process quality deteriorates due to step differences
Solution Approach 1:
The patent applies asymmetry by designing dummy pads with non-uniform surface areas that gradually decrease from larger sizes near the electrode pads to smaller sizes toward the insulating layer edge. This asymmetric configuration optimizes CMP process quality by providing graduated protection against erosion and squeeze out, while still maintaining relatively simple manufacturing through standard photolithography and etching processes.
Data Source
AI summary
A semiconductor package includes: a first structure having a first insulating layer disposed on one surface, and first electrode pads and first dummy pads penetrating through the first insulating layer, a second structure having a second insulating layer having the other surface bonded to the one surface and the first insulating layer and disposed on the other surface, and second electrode pads and second dummy pads that penetrate through the second insulating layer, the second electrode pads being bonded to the first electrode pads, respectively, and the second dummy pads being bonded to the first dummy pads, respectively. In the semiconductor chip, ratios of surface areas per unit area of the first and second dummy pads to the first and second insulating layers on the one surface and the other surface gradually decrease toward sides of the first and second structures.