Semiconductor Package Dummy Pattern for Dielectric Flatness

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing semiconductor packages face challenges in reliability due to issues such as dishing and undulation of dielectric layers, which can lead to process defects and reduced durability.

Innovation Solution

The semiconductor package incorporates a dummy pattern spaced apart from the under bump, with the dummy pattern penetrating the second dielectric layer and contacting the first dielectric layer, and an interval between the under bump and the dummy pattern ranging from about 5 μm to about 50 μm, which helps in increasing the flatness of the dielectric layers and preventing process defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional semiconductor package structures are used without dummy patterns, then the manufacturing process is simpler, but dishing and undulation of dielectric layers occur leading to reduced reliability

Engineering Contradiction:
Improvepackage reliabilityVSAvoidsubstrate structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The dummy pattern is created as a copy of the under bump structure, replicating its shape and material composition. This copy serves to mimic the mechanical support function of the under bump without carrying electrical signals, thereby preventing dishing and undulation in dielectric layers while maintaining process simplicity

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The dummy pattern modifies the physical parameters of the substrate structure by adding additional support elements with specific dimensions (interval of 5-50 μm from under bump). This changes the mechanical stiffness distribution in the dielectric layers, preventing deformation during packaging processes

Inventive Principle:
Principle #35Parameter changes

2Strength

If the dummy pattern is placed too close to the under bump, then better structural support is achieved, but process defects may occur due to insufficient spacing

Engineering Contradiction:
Improvedielectric layer flatnessVSAvoidprocess defect rate
Core Design Contradiction:
StrengthVSManufacturing precision

Solution Approach 1:

The interval between the under bump and dummy pattern is optimized to a specific range (5-50 μm). This parameter optimization ensures sufficient spacing to avoid process defects such as bridging or contamination during manufacturing, while maintaining close proximity to provide effective mechanical support and prevent dishing

Inventive Principle:
Principle #35Parameter changes

3Strength

If the dummy pattern fully penetrates through all dielectric layers, then maximum structural support is provided, but material consumption and processing complexity increase

Engineering Contradiction:
Improvemechanical support strengthVSAvoidmaterial consumption
Core Design Contradiction:
StrengthVSLoss of substance

Solution Approach 1:

The dummy pattern is designed with local quality by extending only to the first dielectric layer rather than penetrating through all dielectric layers. This localized structure provides sufficient mechanical support at the critical interface where dishing occurs, while reducing unnecessary material consumption in upper dielectric layers

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12211777B2Semiconductor package including a dummy pattern
Publication Date: 2025.01.28 SAMSUNG ELECTRONICS CO LTD
  • US12211777B2 patent drawing
  • US12211777B2 patent drawing
  • US12211777B2 patent drawing

AI summary

A semiconductor package including: a first substrate and a semiconductor device on the first substrate, wherein the first substrate includes: a first dielectric layer including a first hole; a second dielectric layer on the first dielectric layer and including a second hole that overlaps the first hole, the second hole being wider than the first hole; an under bump disposed in the first hole and the second hole, the under bump covering a portion of the second dielectric layer; and a connection member bonded to the under bump.