Semiconductor Package Layout Using Dummy Posts Against CTE Warpage
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Solution Overview
Problem
Existing semiconductor packages face challenges in miniaturization and weight reduction while maintaining high-capacity data processing, leading to issues such as warpage due to coefficient of thermal expansion (CTE) mismatch during manufacturing.
Innovation Solution
The semiconductor package incorporates a side-by-side memory package and a logic package, with the logic package featuring dummy posts that are electrically insulated and extend into a molding member, adjusting the CTE and improving structural stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor packages are miniaturized and stacked to increase capacity, then data processing capacity is improved, but warpage occurs due to CTE mismatch during manufacturing
Solution Approach 1:
The patent introduces dummy posts with specific material properties (different CTE from surrounding materials) to change the thermal expansion parameters of the package structure. These dummy posts are strategically positioned to compensate for CTE mismatch between different components, thereby preventing warpage while maintaining the miniaturized stacked configuration for high-capacity data processing
Solution Approach 2:
The patent employs a composite structure consisting of multiple materials with different CTE values (molding compound, dummy posts, semiconductor chips, substrate). By carefully selecting and combining these materials, the overall package achieves thermal expansion compatibility across temperature variations, resolving the warpage issue inherent in miniaturized multi-chip packages
2Volume of moving object
If multiple semiconductor chips are stacked to reduce volume, then package volume is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the package into modular segments (substrate, multiple semiconductor chips, molding compound, dummy posts) that can be manufactured and prepared separately before final assembly. This segmentation allows each component to be optimized independently while simplifying the overall manufacturing process through standardized interfaces and assembly procedures
Solution Approach 2:
The dummy posts serve as intermediary elements between the semiconductor chips and molding compound. These posts facilitate the molding process by providing structural support and controlling material flow, thereby simplifying the manufacturing of multi-chip stacked packages while maintaining compact volume
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the semiconductor package to prevent warpage caused by CTE mismatch, enhance structural stability, and improve heat dissipation properties, while maintaining high-capacity data processing in a compact form.
Implementation Method 1
warpage due to coefficient of thermal expansion (CTE) mismatch during manufacturing
Implementation Method 2
one or more dummy posts extending into the molding member in a vertical direction and configured to be electrically insulated
Data Source
AI summary
Provided is a semiconductor package including a first substrate, a first semiconductor package on the first substrate and including a first semiconductor chip, and a second semiconductor package on the first substrate spaced apart from the first semiconductor package in a horizontal direction, and including one or more semiconductor chips and a molding layer on the one or more semiconductor chips, wherein the molding layer includes a molding member and one or more dummy posts extending into the molding member in a vertical direction and configured to be electrically insulated.