Semiconductor Package UBM Dummy Space for Stress-Relieved Interconnects

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Solution Overview

Problem

Existing semiconductor packages face challenges in achieving both structural reliability and a short electrical connection path between the chip pad and the connection terminal.

Innovation Solution

The semiconductor package incorporates a redistribution pattern with a dummy space and an under bump metal (UBM) structure that includes dummy holes, allowing the connection terminal to fill these spaces, thereby distributing stress and improving structural reliability while maintaining a short electrical connection path.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If a direct electrical connection path is implemented between chip pad and connection terminal, then electrical connection length is shortened, but structural reliability deteriorates due to stress concentration

Engineering Contradiction:
Improveelectrical connection path lengthVSAvoidstructural reliability
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

The connection terminal is divided into functional segments: an active connection portion for electrical connection and a dummy portion for stress absorption. This segmentation allows the terminal to simultaneously achieve short electrical path length and improved structural reliability by distributing fabrication stress away from the critical connection region.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The dummy portion of the connection terminal acts as an intermediary element between the active connection region and the external environment. It absorbs fabrication stress that would otherwise concentrate on the short electrical connection path, thereby protecting the integrity of the electrical connection while maintaining the shortened path design.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If stress distribution structures are added to improve structural reliability, then manufacturing complexity increases

Engineering Contradiction:
Improvestructural reliabilityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The stress distribution function is merged with the existing connection terminal structure by adding a dummy portion to the terminal itself. This integration approach avoids introducing separate, complex stress management components while still achieving effective stress distribution across the package structure.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The connection terminal is designed to perform multiple functions: establishing electrical connection through its active portion and distributing fabrication stress through its dummy portion. This multi-functionality reduces the need for additional dedicated stress management structures, thereby limiting the increase in manufacturing complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250105187A1Semiconductor package
Publication Date: 2025.03.27 SAMSUNG ELECTRONICS CO LTD
  • US20250105187A1 patent drawing
  • US20250105187A1 patent drawing
  • US20250105187A1 patent drawing

AI summary

A semiconductor package includes: a semiconductor chip including a chip pad on a first surface; a first insulating layer arranged on the semiconductor chip and including an insulating hole exposing the chip pad; a redistribution pattern including a redistribution via pattern arranged on an internal surface of the first insulating layer configured to define the first insulating hole and on a surface of the chip pad, and a redistribution line pattern arranged on a surface of the first insulating layer; an under bump metal (UBM) conformally arranged along a surface of the redistribution pattern; and a connection terminal arranged on the UBM, wherein the redistribution line pattern and the UBM provide a dummy space of a shape protruding in a direction toward the first surface of the semiconductor chip, and a portion of the connection terminal fills the dummy space.