Semiconductor Package Layout Using Dummy TIVs for Void Control
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving uniform encapsulation and preventing delamination and void formation during the molding process, particularly with the use of smaller components that require smaller packages.
Innovation Solution
The introduction of a dual-layer redistribution structure with active and dummy through-insulating vias (TIVs) that utilize conductive pillars to enhance flow uniformity and stress relief during encapsulation, ensuring uniform distribution of molding material and reducing the risk of voids and delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional single-layer redistribution structures are used, then device complexity is reduced, but encapsulation uniformity deteriorates leading to voids and delamination
Solution Approach 1:
The redistribution structure is divided into two separate layers: a first redistribution layer and a second redistribution layer. This segmentation allows each layer to be independently optimized for specific functions - the first layer handles signal routing while the second layer provides encapsulation support, thereby improving encapsulation uniformity without requiring excessive complexity in a single layer.
Solution Approach 2:
The patent transitions from a conventional single-layer (2D) redistribution structure to a dual-layer (3D) configuration. By adding the vertical dimension with stacked redistribution layers, the structure achieves better encapsulation uniformity and stress distribution while maintaining manageable complexity through functional separation.
2Productivity
If smaller packages are used for smaller components, then integration density is improved, but encapsulation reliability deteriorates due to increased risk of voids and delamination
Solution Approach 1:
The first redistribution layer is formed and configured before the second redistribution layer and encapsulation process. This preliminary configuration establishes a stable base structure with proper stress distribution characteristics, preventing void formation and delamination during subsequent encapsulation of smaller components in high-density configurations.
Solution Approach 2:
The patent employs a composite redistribution structure combining two distinct layers with different functional optimizations. The first layer uses specific material properties for signal routing, while the second layer incorporates materials and structures optimized for encapsulation support, creating a composite system that maintains reliability in smaller packages.
Data Source
AI summary
A manufacturing method of a semiconductor package includes: forming an insulating encapsulation on a backside redistribution structure to laterally cover a semiconductor die, active TIVs, and dummy TIVs on the backside redistribution structure; and forming a front-side redistribution structure on an active surface of the semiconductor die, the insulating encapsulation, the active TIVs, and the dummy TIVs. The semiconductor die is electrically coupled to the backside redistribution structure through the front-side redistribution structure and the active TIVs. The dummy TIVs are electrically floating. In a top view, the dummy TIVs are disposed along package edges, the active TIVs are arranged in active regions of the semiconductor package disposed adjacent to the semiconductor die, and the dummy TIVs are distributed beside the active regions.