Semiconductor Package Edge Ball Array for Crack-Tolerant Power Supply

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Solution Overview

Problem

The increasing size of semiconductor chips and packages to meet high-performance demands conflicts with the desire for thinner devices, and existing semiconductor packages face reliability issues due to cracks in solder balls that supply power to passive elements, leading to defects in electrical connections.

Innovation Solution

A semiconductor package design featuring a ball array region with multiple power solder balls adjacent to passive elements, ensuring continued electrical connectivity even if cracks occur in some solder balls, thereby enhancing the reliability of the electrical connection relationship.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the size of semiconductor chip and package is increased to meet high-performance demands, then performance is improved, but the thickness of the device increases

Engineering Contradiction:
ImproveperformanceVSAvoidthickness
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The patent transitions from a traditional single-sided ball array to a dual-sided configuration with ball arrays on both the upper and lower surfaces of the substrate. This dimensional change allows electrical connections to be established in multiple directions, enabling high-performance connectivity without increasing the overall package thickness.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If solder balls are used to supply power to passive elements, then electrical connection is established, but cracks in solder balls lead to reliability defects

Engineering Contradiction:
Improveelectrical connectionVSAvoidcracks in solder balls
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent creates a dedicated edge region with a concentrated array of solder balls specifically positioned adjacent to passive elements. This local quality enhancement ensures that critical power supply connections are reinforced with multiple solder balls in strategic locations, providing redundancy against crack-induced failures while maintaining overall package reliability.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent pre-positiones multiple solder balls in the edge region adjacent to passive elements before any cracks can occur. This beforehand cushioning creates a redundant connection system where multiple solder balls serve as backup pathways, ensuring that if some solder balls develop cracks, electrical connectivity is maintained through the remaining intact solder balls.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Reliability

If multiple power solder balls are placed adjacent to passive elements, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidball array configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the substrate into distinct functional regions: a ball array region containing the solder ball arrays, a passive element region, and an external region. This segmentation organizes the multiple solder balls into structured arrays with defined patterns, making the complex configuration more manageable and easier to manufacture while maintaining the reliability benefits of multiple power solder balls adjacent to passive elements.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240234274A1Semiconductor package including an edge region having a plurality of solder balls therein
Publication Date: 2024.07.11 SAMSUNG ELECTRONICS CO LTD
  • US20240234274A1 patent drawing
  • US20240234274A1 patent drawing
  • US20240234274A1 patent drawing

AI summary

A semiconductor package, including a first structure including a ball array region on a lower surface of the first structure and an external region completely surrounding the ball array region, the ball array region including a passive element region in which solder balls are not disposed and an edge region completely surrounding the passive element region, a first semiconductor chip on an upper surface of the first structure, a passive element in the passive element region on the lower surface of the first structure, the passive element not in the edge region on the lower surface of the first structure, and a first ball array in the edge region on the lower surface of the first structure, the first ball array including two or more first power solder balls supplying power to at least one of the passive element and the first semiconductor chip.