Semiconductor Package Edge Capacitor Placement for Power Integrity
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving improved power integrity and efficient power supply, particularly in high-speed portable electronic devices, due to spatial limitations and the need for uninterrupted power delivery.
Innovation Solution
The semiconductor package design optimizes the internal layout by positioning core power units adjacent to the edges of the integrated circuit chip and placing capacitors nearby, with a redistribution layer and encapsulant to enhance power integrity and reduce equivalent series inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If capacitors are placed far from power-consuming units due to spatial limitations, then device integration is improved, but power integrity deteriorates
Solution Approach 1:
The patent utilizes the vertical dimension by placing capacitors on the back surface of the substrate opposite to the integrated circuit chip. This three-dimensional arrangement allows capacitors to be positioned close to power-consuming units in terms of electrical path length while maintaining compact horizontal footprint, thereby improving power integrity without compromising device integration.
Solution Approach 2:
The substrate is divided into front and back surfaces with distinct functional assignments. The front surface hosts the integrated circuit chip while the back surface accommodates capacitors. This segmentation allows independent optimization of each surface's layout, enabling capacitors to be positioned optimally for power delivery while the front surface maintains high integration density.
2Adaptability or versatility
If connection paths between capacitors and power units are lengthened, then layout flexibility is improved, but impedance characteristics worsen
Solution Approach 1:
By transitioning to vertical stacking in the third dimension, the electrical connection path between capacitors and power units is significantly shortened despite increased layout flexibility. The redistribution layers provide direct vertical interconnects, minimizing path length and maintaining low impedance while allowing flexible horizontal placement options.
Solution Approach 2:
Redistribution layers serve as intermediary conductive structures that efficiently connect capacitors on the back surface to power units on the front surface. These intermediary layers optimize the electrical path, maintaining low impedance characteristics while enabling flexible layout arrangements through their routing capabilities.
3Area of stationary object
If capacitors are positioned away from edges to maximize chip utilization, then area efficiency is improved, but power supply stability deteriorates
Solution Approach 1:
The solution moves capacitor placement to the back surface dimension, allowing edge-adjacent positioning that optimizes power supply stability through short connection paths to edge-located power units, while the front surface maintains maximum area efficiency for high-density circuit integration.
Solution Approach 2:
Different regions of the substrate are assigned different functions: the front surface optimizes for high-density integration while the back surface optimizes for power supply stability. This local quality differentiation allows each surface to be optimized for its specific function without compromising the other.
Data Source
AI summary
A semiconductor package includes a connection member having first and second surfaces opposing each other and including a redistribution layer, an integrated circuit chip disposed on the first surface of the connection member, and including a plurality of units, at least one capacitor on the first surface of the connection member and in proximity to the integrated circuit chip, and an encapsulant on the first surface of the connection member and encapsulating the integrated circuit chip and the at least one capacitor, wherein the plurality of units include core power units selected from the group consisting of a central processing unit, a graphics processing unit, and an artificial intelligence unit, at least one of the core power units is disposed adjacent to one edge of the integrated circuit chip, and the at least one capacitor is disposed adjacent to the one edge of the integrated circuit chip.